short-paper

Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation

Authors:

Michihiro Shintani,

Shumpei Morita,

Hiromitsu Awano,

Masayuki Hiromoto,

Takashi SatoAuthors Info & Claims

GLSVLSI '16: Proceedings of the 26th edition on Great Lakes Symposium on VLSI

Pages 203 - 208

https://doi.org/10.1145/2902961.2903013

Published: 18 May 2016 Publication History

Abstract

As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. In addition, aging mechanisms like the negative bias temperature instability (NBTI) is known to be sensitive to workload (i.e., signal probability) that is hard to be assumed at design phase. In this work, we analyze the workload dependence of NBTI degradation using a processor, and propose a novel technique to estimate the worst-case paths. In our approach, with careful examination, we exploit the fact that the deterministic nature of circuit structure limits the amount of NBTI degradation on different paths, and proposes a two-stage path extraction algorithm to identify the invariable critical paths in the processor. Through numerical experiment on a MIPS32 processor, we performed a detailed signal probability analysis, and successfully extracted 85 invariable critical paths out of the 24,978 path candidates, achieving nearly 300x reduction in the sheer number of paths.

References

[1]

OpenCores. http://www.opencores.org

[2]

A. Abdollahi, F. Fallah, and M. Pedram. Leakage current reduction in CMOS VLSI circuits by input vector control. IEEE Trans. VLSI Systems, 12(2):140--154, 2004.

Digital Library

[3]

D. Arthur and S. Vassilvitskii. k-means++: The advantages of careful seeding. In Proc. ACM-SIAM Symp. Discrete Algorithms, pages 1027--1035, 2007.

Digital Library

[4]

H. Awano, M. Hiromoto, and T. Sato. BTIarray: a time-overlapping transistor array for efficient statistical characterization of bias temperature instability. IEEE Trans. Dev. Mater. Rel., 14(3):833--843, 2014.

[5]

R. Baranowski et al. On-line prediction of NBTI-induced aging rates. In Proc. DATE, pages 589--592, 2015

Digital Library

[6]

S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, and S. Vrudhula. Predictive modeling of the NBTI effect for reliable design. In Proc. CICC, pages 189--192, 2006.

[7]

S. Bian, M. Shintani, S. Morita, M. Hiromoto, and T. Sato. Nonlinear delay-table approach for full-chip NBTI degradation prediction. In Proc. ISQED, pages 307--312, 2016.

[8]

D. R. Bild, R. P. Dick, and G. E. Bok. Static NBTI reduction using internal node control. ACM TODAES, 17(4):45--75, 2012.

Digital Library

[9]

C. Chavet et al. A design ow dedicated to multi-mode architectures for DSP applications. In Proc. ICCAD, pages 604--611, 2007

Digital Library

[10]

M. Ebrahimi, F. Oboril, S. Kiamehr, and M. B. Tahoori. Aging-aware logic synthesis. In Proc. ICCAD, pages 61--68, 2013.

Digital Library

[11]

M. Guthaus et al. MiBench: A free, commercially representative embedded benchmark suite. In Proc. WWC, pages 3--14, 2001

Digital Library

[12]

L. Hamers et al. Similarity measures in scientometric research: the Jaccard index versus Salton's cosine formula. Information Processing & Management, 25(3):315--318, 1989.

Digital Library

[13]

A. Koneru, A. Vijayan, K. Chakrabarty, and M. B. Tahoori. Fine-grained aging prediction based on the monitoring of run-time stress using DfT infrastructure. In Proc. ICCAD, pages 51--58, 2015.

Digital Library

[14]

H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye. Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration. In Proc. ISQED, pages 646--651, 2010.

[15]

J. A. Kumar, K. M. Butler, H. Kim, and S. Vasudevan. Early prediction of NBTI effects using RTL source code analysis. In Proc. DAC, pages 808--813, 2012.

Digital Library

[16]

D. Lorenz, G. Georgakos, and U. Schlichtmann. Aging analysis of circuit timing considering NBTI and HCI. In Proc. IOLTS, pages 3--8, 2009.

[17]

Mentor Graphics, Inc. ModelSim SE 10.2c.

[18]

F. N. Najm. A survey of power estimation techniques in VLSI circuits. IEEE Trans. VLSI Systems, 2:446--455, 1994.

Digital Library

[19]

Si2.org. Nangate 45nm open cell library. http://www.si2.org.

[20]

A. Stempkovsky, A. Glebov, and S. Gavrilov. Calculation of stress probability for NBTI-aware timing analysis. In Proc. ISQED, pages 714--718, 2009.

Digital Library

[21]

Synopsys, Inc. Design Compiler I-2013.06.

[22]

Synopsys, Inc. PrimeTime Fundamental H-2013.06.

[23]

Synopsys, Inc. PrimeTime PX H-2013.06.

Cited By

Zhang YTang ZJin YZhang HSun YChen CLin XLi CYou H(2024)An Efficient Aged Timing Analysis Method for Digital Integrated Circuit Under NBTI Effect2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617875(474-479)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617875
Acharya LKumar Sharma AMishra NSingh KDargupally MShabarish NMandal ARamakrishnan VDasgupta SBulusu A(2023)Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical EffortIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.323117342:8(2657-2663)Online publication date: 1-Aug-2023
https://dl.acm.org/doi/10.1109/TCAD.2022.3231173
Morita SBian SShintani MSato T(2022)Efficient Analysis for Mitigation of Workload-Dependent Aging DegradationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.314985641:12(5515-5525)Online publication date: Dec-2022
https://doi.org/10.1109/TCAD.2022.3149856
Show More Cited By

Index Terms

Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation
1. Hardware

Recommendations

Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits
ISLPED '11: Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design

Device aging, which causes significant loss on circuit performance and lifetime, has been a main factor in reliability degradation of nanoscale designs. Aggressive technology scaling trends, such as thinner gate oxide without proportional downscaling of ...
NBTI-aware flip-flop characterization and design
GLSVLSI '08: Proceedings of the 18th ACM Great Lakes symposium on VLSI

With the scaling down of the CMOS technologies, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the corresponding reduction in the long-term reliability of CMOS circuits. ...
TG-based technique for NBTI degradation and leakage optimization
ISLPED '11: Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design

Abstract NBTI (Negative Bias Temperature Instability), which can degrade the switching speed of PMOS transistors, has become a major reliability challenge. Meanwhile, reducing leakage consumption has become major design goals. In this paper, we propose ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

GLSVLSI '16: Proceedings of the 26th edition on Great Lakes Symposium on VLSI

May 2016

462 pages

ISBN:9781450342742

DOI:10.1145/2902961

General Chairs:
Ayse K. Coskun
Boston University, USA
,
Martin Margala
University of Massachusetts, Lowell, USA
,
Program Chairs:
Laleh Behjat
University of Calgary, Canada
,
Jie Han
University of Alberta, Canada

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE CEDA
IEEE CASS

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 May 2016

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Short-paper

Funding Sources

Japan Society for the Promotion of Science

Conference

GLSVLSI '16

Sponsor:

SIGDA

GLSVLSI '16: Great Lakes Symposium on VLSI 2016

May 18 - 20, 2016

Massachusetts, Boston, USA

Acceptance Rates

GLSVLSI '16 Paper Acceptance Rate 50 of 197 submissions, 25%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

13
Total Citations
View Citations
131
Total Downloads

Downloads (Last 12 months)9
Downloads (Last 6 weeks)0

Reflects downloads up to 13 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Zhang YTang ZJin YZhang HSun YChen CLin XLi CYou H(2024)An Efficient Aged Timing Analysis Method for Digital Integrated Circuit Under NBTI Effect2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617875(474-479)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617875
Acharya LKumar Sharma AMishra NSingh KDargupally MShabarish NMandal ARamakrishnan VDasgupta SBulusu A(2023)Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical EffortIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.323117342:8(2657-2663)Online publication date: 1-Aug-2023
https://dl.acm.org/doi/10.1109/TCAD.2022.3231173
Morita SBian SShintani MSato T(2022)Efficient Analysis for Mitigation of Workload-Dependent Aging DegradationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.314985641:12(5515-5525)Online publication date: Dec-2022
https://doi.org/10.1109/TCAD.2022.3149856
Zhang ZWang RShen XWu DZhang JZhang ZWang JHuang R(2021)Aging-Aware Gate-Level Modeling for Circuit Reliability AnalysisIEEE Transactions on Electron Devices10.1109/TED.2021.309617168:9(4201-4207)Online publication date: Sep-2021
https://doi.org/10.1109/TED.2021.3096171
Raji MMahmoudi RGhavami BKeshavarzi S(2021)Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage AssignmentIEEE Access10.1109/ACCESS.2021.31032009(114120-114134)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3103200
Gomez AChampac V(2019)An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging EffectsJournal of Electronic Testing: Theory and Applications10.1007/s10836-019-05772-535:1(87-100)Online publication date: 15-May-2019
https://dl.acm.org/doi/10.1007/s10836-019-05772-5
Morita SBian SShintani MHiromoto MSato TShin Y(2018)Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradationProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201753(631-636)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.5555/3201607.3201753
Duan SZwolinski MHalak B(2018)Lifetime Reliability-Aware Digital SynthesisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.286182026:11(2205-2216)Online publication date: Nov-2018
https://doi.org/10.1109/TVLSI.2018.2861820
Gomez AGomez RChampac V(2018)A metric-guided gate-sizing methodology for aging guardband reduction2018 IEEE 19th Latin-American Test Symposium (LATS)10.1109/LATW.2018.8349677(1-6)Online publication date: Mar-2018
https://doi.org/10.1109/LATW.2018.8349677
Shin ZMorita SBian SShintani MHiromoto MSato T(2018)A study on NBTI-induced delay degradation considering stress frequency dependence2018 19th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2018.8357296(251-256)Online publication date: Mar-2018
https://doi.org/10.1109/ISQED.2018.8357296
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents