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WiSync: An Architecture for Fast Synchronization through On-Chip Wireless Communication

Authors:

Albert Cabellos-Aparicio,

Eduard Alarcon,

Josep TorrellasAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 44, Issue 2

Pages 3 - 17

https://doi.org/10.1145/2980024.2872396

Published: 25 March 2016 Publication History

Abstract

In shared-memory multiprocessing, fine-grain synchronization is challenging because it requires frequent communication. As technology scaling delivers larger manycore chips, such pattern is expected to remain costly to support. In this paper, we propose to address this challenge by using on-chip wireless communication. Each core has a transceiver and an antenna to communicate with all the other cores. This environment supports very low latency global communication. Our architecture, called WiSync, uses a per-core Broadcast Memory (BM). When a core writes to its BM, all the other 100+ BMs get updated in less than 10 processor cycles. We also use a second wireless channel with cheaper transfers to execute barriers efficiently. WiSync supports multiprogramming, virtual memory, and context switching. Our evaluation with simulations of 128-threaded kernels and 64-threaded applications shows that WiSync speeds-up synchronization substantially. Compared to using advanced conventional synchronization, WiSync attains an average speedup of nearly one order of magnitude for the kernels, and 1.12 for PARSEC and SPLASH-2.

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Index Terms

WiSync: An Architecture for Fast Synchronization through On-Chip Wireless Communication
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data

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Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 44, Issue 2

ASPLOS'16

May 2016

774 pages

ISSN:0163-5964

DOI:10.1145/2980024

Editor:
Doug DeGroot
acm dot org

Issue’s Table of Contents

ASPLOS '16: Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems
March 2016
824 pages
ISBN:9781450340915
DOI:10.1145/2872362
General Chair:
Tom Conte
Georgia Tech, USA
,
Program Chair:
Yuanyuan Zhou
University of California, San Diego, USA

Copyright © 2016 ACM.

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Published: 25 March 2016

Published in SIGARCH Volume 44, Issue 2

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Cited By

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https://doi.org/10.5772/intechopen.1005621
Abadal SHan CPetrov VGalluccio LAkyildiz IJornet J(2024)Electromagnetic Nanonetworks Beyond 6G: From Wearable and Implantable Networks to On-Chip and Quantum CommunicationIEEE Journal on Selected Areas in Communications10.1109/JSAC.2024.339925342:8(2122-2142)Online publication date: 1-Aug-2024
https://dl.acm.org/doi/10.1109/JSAC.2024.3399253
Damsgaard HOmetov ANurmi J(2023)Approximation Opportunities in Edge Computing Hardware: A Systematic Literature ReviewACM Computing Surveys10.1145/357277255:12(1-49)Online publication date: 3-Mar-2023
https://dl.acm.org/doi/10.1145/3572772
Yazdanpanah FAfsharmazayejani R(2022)A systematic analysis of power saving techniques for wireless network-on-chip architecturesJournal of Systems Architecture10.1016/j.sysarc.2022.102485126(102485)Online publication date: May-2022
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