research-article

Efficient and accurate analysis of Single Event Transients propagation using SMT-based techniques

Authors:

Ghaith Bany Hamad,

Otmane Ait Mohamed,

Yvon SavariaAuthors Info & Claims

2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Pages 1 - 7

https://doi.org/10.1145/2966986.2967027

Published: 07 November 2016 Publication History

Abstract

This paper presents a hierarchical framework to model, analyze, and estimate digital design vulnerability to soft errors due to Single Event Transients (SETs). A new SET propagation model is proposed. This model simultaneously includes the impact of masking effects, width variation, and re-converging paths by utilizing satisfiability modulo theories. Furthermore, new metrics characterizing the soft error rate of a given design are proposed. Reported results show that the proposed methodology significantly enhances the efficiency of SET analysis in terms of: 1) accuracy as it gives accurate estimates of SET sensitivity based on gates timing extracted from layout. These results provide new insights to combinational designs vulnerability to SETs; 2) speed as it is orders of magnitude faster than contemporary techniques; 3) scalability as it can handle large and complex designs such as 128-bit multipliers, whereas contemporary techniques are unable to handle multipliers larger than 32 bits.

5. References

[1]

T. Zaremba et al. Radiotherapy in patients with pacemakers and implantable cardioverter defibrillators: a literature review. Europace Journal, pages 135–145, 2015.

[2]

V. Ferlet-Cavrois et al. Investigation of the propagation induced pulse broadening (PIPB) effect on single event transients in soi and bulk inverter chains. IEEE Trans. Nucl. Sci, 55 (6): 2842–2853, 2008.

[3]

G. Wirth et al. Single event transients in logic circuits load and propagation induced pulse broadening. IEEE Trans. Nucl. Sci, 55 (6): 2928–2935, 2008.

[4]

J. Baraza, J. Gracia, S. Blanc, D. Gil, and P. Gil. Enhancement of fault injection techniques based on the modification of VHDL code. IEEE Trans. on Very Large Scale Integration (TVLSI), 16 (6): 693–706, 2008.

Digital Library

[5]

K. Basu et al. Observability-aware directed test generation for soft errors and crosstalk faults. In VLSID, pages 291–296, 2013.

[6]

Feng Wang and Yuan Xie. Soft error rate analysis for combinational logic using an accurate electrical masking model. Dependable and Secure Computing, IEEE Transactions on, 8 (1): 137–146, 2011.

Digital Library

[7]

Y. Kuo et al. Accurate statistical soft error rate (sser) analysis using a quasi-monte carlo framework with quality cell models. In ISQED, pages 831–838, 2010.

[8]

R. Rajaraman et al. Seat-la: a soft error analysis tool for combinational logic. In 19th International Conference on VLSI Design, pages 4–8. IEEE, 2006.

[9]

M. Zhang et al. Soft-error-rate-analysis (sera) methodology. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25 (10): 2140–2155, 2006.

Digital Library

[10]

N. Miskov-Zivanov and D. Marculescu. Mars-c: modeling and reduction of soft errors in combinational circuits. In DAC, pages 767–772, 2006.

[11]

J. Kumar. Statistical guarantees of performance for RTL designs. 2012.

[12]

G. Bany Hamad et al. Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits. Microelectronics Reliability, 55 (1): 238–250, 2015.

[13]

Synopsys HSPICE. Inc, dec. 2010. Version E-2010.12.

[14]

A. Daga et al. Automated timing model generation. In Proceedings of Design Automation Conference (DAC), pages 146–151, 2002.

[15]

C. Loiacono et al. Fast cone-of-influence computation and estimation in problems with multiple properties. In DATE, pages 803–806, 2013.

[16]

J. Han et al. Reliability evaluation of logic circuits using probabilistic gate models. Microelectronics Reliability, 51 (2): 468–476, 2011.

[17]

J. Stine et al. Freepdk: An open-source variation-aware design kit. In IEEE ICMS, pages 173–174, 2007.

[18]

D. Limbrick et al. Reliability-aware synthesis of combinational logic with minimal performance penalty. IEEE Transactions on Nuclear Science, 60 (4): 2776–2781, 2013.

Cited By

Seghaier IZaki MTahar S(2020)Mating Sensitivity Analysis and Statistical Verification for Efficient Yield EstimationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288976439:2(294-307)Online publication date: Feb-2020
https://doi.org/10.1109/TCAD.2018.2889764
Atallah AHamad GMohamed O(2019)Reliability Analysis of TSN Networks Under SEU Induced Soft Error Using Model Checking2019 IEEE Latin American Test Symposium (LATS)10.1109/LATW.2019.8704633(1-6)Online publication date: Mar-2019
https://doi.org/10.1109/LATW.2019.8704633
Kazma GHamad GMohamed OSavaria YBehjat LHan JVelev MChen D(2017)Analysis of SEU Propagation in Combinational Circuits at RTL Based on Satisfiability Modulo TheoriesProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060438(239-244)Online publication date: 10-May-2017
https://dl.acm.org/doi/10.1145/3060403.3060438
Show More Cited By

Index Terms

Efficient and accurate analysis of Single Event Transients propagation using SMT-based techniques
1. Hardware

Index terms have been assigned to the content through auto-classification.

Recommendations

Single event transients in dynamic logic
SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design

Radiation effects, like Single Event Transients (SET), are increasingly affecting integrated circuits as device dimensions are scaling down. With decreasing dimensions and supply voltages, the charge used to store information decreases, turning the ...
A physics-based analytical model for single-event transients in an InGaAs n-channel FinFET suitable for circuit simulations
Abstract
InGaAs/Ge complementary FinFET technology has been considered as an alternative channel material for CMOS technology, useful for next-generation digital VLSI circuits. The soft errors in these C-FinFETs are dominated by the ion strike at the ...
Circuit-Level Simulation of the Single Event Transients in an On-Chip Single Event Latchup Protection Switch

The circuit-level simulation analysis of the single event transient response of an on-chip single event latchup protection switch (SPS cell), previously designed and developed in the IHP 250 nm CMOS process, is presented. The SPS cell provides the ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image Guide Proceedings

2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Nov 2016

946 pages

Copyright © 2016.

Publisher

IEEE Press

Publication History

Published: 07 November 2016

Permissions

Request permissions for this article.

Request Permissions

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

4
Total Citations
View Citations
81
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 21 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Seghaier IZaki MTahar S(2020)Mating Sensitivity Analysis and Statistical Verification for Efficient Yield EstimationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288976439:2(294-307)Online publication date: Feb-2020
https://doi.org/10.1109/TCAD.2018.2889764
Atallah AHamad GMohamed O(2019)Reliability Analysis of TSN Networks Under SEU Induced Soft Error Using Model Checking2019 IEEE Latin American Test Symposium (LATS)10.1109/LATW.2019.8704633(1-6)Online publication date: Mar-2019
https://doi.org/10.1109/LATW.2019.8704633
Kazma GHamad GMohamed OSavaria YBehjat LHan JVelev MChen D(2017)Analysis of SEU Propagation in Combinational Circuits at RTL Based on Satisfiability Modulo TheoriesProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060438(239-244)Online publication date: 10-May-2017
https://dl.acm.org/doi/10.1145/3060403.3060438
Seghaier ITahar S(2017)Intertwined Global Optimization Based Reachability AnalysisVerification and Evaluation of Computer and Communication Systems10.1007/978-3-319-66176-6_10(139-154)Online publication date: 15-Aug-2017
https://doi.org/10.1007/978-3-319-66176-6_10

View Options

View options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents