research-article

Practical statistical static timing analysis with current source models

Authors:

Vladimir Zolotov,

Sheshashayee K. Raghunathan,

Michael H. Wood,

Kerim KalafalaAuthors Info & Claims

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

Article No.: 113, Pages 1 - 6

https://doi.org/10.1145/2897937.2898068

Published: 05 June 2016 Publication History

Abstract

This paper considers the practical nuances of using current source gate models in an industrial statistical timing analysis environment. Specifically, the memory overhead of a naive implementation combining statistical and current source models to obtain and store gate output waveforms is found to be impractical for large microprocessor designs. A study is performed to observe variational gate output waveforms, and a technique is presented to store the waveforms in a memory efficient manner with minimal accuracy impact. The presented technique is validated over a set of 14 nanometer designs, and has enabled the usage of current source models in our industrial statistical timing analysis flow. Results demonstrate slack accuracy improvements of up to 17 picoseconds with a 1.15X run-time overhead and 1.1 gigabytes per million-gates memory overhead in comparison to an existing flow.

References

[1]

J. Qian, S. Pullela, and L. T. Pillage, "Modeling the effective capacitance for the RC interconnect of CMOS gates," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 12, 1994, pp. 1526--1535.

Digital Library

[2]

I. Keller, K. Tseng, and N. Verghese, "A robust cell-level crosstalk delay change analysis," in ICCAD, 2004, pp. 147--154.

Digital Library

[3]

J. F. Croix and D. F. Wong, "Blade and razor: cell and interconnect delay analysis using current-based models," in DAC, 2003, pp. 386--389.

Digital Library

[4]

P. Li and E. Acar, "A waveform independent gate model for accurate timing analysis," in ICCAD, 2005, pp. 363--365.

Digital Library

[5]

C. Kashyap, C. Amin, N. Menezes, and E. Chiprout, "A nonlinear cell macromodel for digital applications," in ICCAD, 2007, pp. 678--685.

Digital Library

[6]

Cadence, Effective current source model library format. cadence.com/Alliances/languages/Pages/ecsm.aspx.

[7]

Synopsys, Composite current source model timing. www.opensourceliberty.org/ccspaper/ccs timingwp.pdf.

[8]

P. Feldmann, S. Abbaspour, D. Sinha, G. Schaeffer, R. Banerji, and H. Gupta, "Driver waveform computation for timing analysis with multiple voltage threshold driver models," in DAC, 2008, pp. 425--428.

Digital Library

[9]

S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, "Parameter variations and impact on circuits and microarchitectures," in DAC, 2003, pp. 338--342.

Digital Library

[10]

C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan, "First-order incremental block-based statistical timing analysis," in DAC, 2004, pp. 331--336.

Digital Library

[11]

L. Zhang, W. Chen, Y. Hu, and C. C. Chen, "Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model," in IEEE Transactions on Computer-Aided Design, 25(6), pp. 1183--1191, June 2006.

Digital Library

[12]

H. Chang, V. Zolotov, S. Narayan, and C. Visweswariah, "Parameterized block-based statistical timing analysis with non-Gaussian parameters, non-linear delay functions," in DAC, 2005, pp. 71--76.

Digital Library

[13]

L. Chen, J. Xiong, and L. He, "Non-Gaussian statistical timing analysis using second-order polynomial fitting," in IEEE Transactions on Computer-Aided Design, vol. 28, no. 1, 2009, pp. 130--140.

Digital Library

[14]

V. Zolotov, D. Sinha, J. Hemmett, E. Foreman, C. Visweswariah, J. Xiong, J. Leitzen, and N. Venkateswaran, "Timing analysis with nonseparable statistical and deterministic variations," in DAC, 2012, pp. 1061--1066.

Digital Library

[15]

S. K. Tiwary and J. R. Phillips, "WAVSTAN: Waveform based variational static timing analysis," in DATE, 2007, pp. 1000--1005.

Digital Library

[16]

S. Gupta and S. S. Sapatnekar, "Compact current source models for timing analysis under temperature and body bias variations," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(11) November 2012, pp. 2104--2117.

Digital Library

[17]

H. Fatemi, S. Nazarian, and M. Pedram, "Statistical logic cell delay analysis using a current-based model," in DAC, 2006, pp. 253--256.

Digital Library

[18]

V. Zolotov, J. Xiong, S. Abbaspour, D. J. Hathaway, and C. Visweswariah, "Compact modeling of variational waveforms," in ICCAD, 2007, pp. 705--712.

Digital Library

[19]

S. Hatami, P. Feldmann, S. Abbaspour, and M. Pedram, "Efficient compression and handling of current source model library waveforms," in DATE, 2009, pp. 1178--1183.

Digital Library

[20]

R. Trihy, "Addressing library creation challanges from recent Liberty extensions," in DAC, 2008, pp. 474--479.

Digital Library

Cited By

Abrishami MGe HCalderon JPedram MNazarian S(2020)NN-PARS: A Parallelized Neural Network Based Circuit Simulation Framework2020 21st International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED48828.2020.9137047(452-456)Online publication date: Mar-2020
https://doi.org/10.1109/ISQED48828.2020.9137047
Abrishami MPedram MNazarian S(2019)CSM-NN: Current Source Model Based Logic Circuit Simulation - A Neural Network Approach2019 IEEE 37th International Conference on Computer Design (ICCD)10.1109/ICCD46524.2019.00061(393-400)Online publication date: Nov-2019
https://doi.org/10.1109/ICCD46524.2019.00061

Index Terms

Practical statistical static timing analysis with current source models
1. Hardware
  1. Hardware validation

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cover image ACM Other conferences

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

June 2016

1048 pages

ISBN:9781450342360

DOI:10.1145/2897937

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 05 June 2016

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DAC '16

DAC '16: The 53rd Annual Design Automation Conference 2016

June 5 - 9, 2016

Texas, Austin

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Cited By

Abrishami MGe HCalderon JPedram MNazarian S(2020)NN-PARS: A Parallelized Neural Network Based Circuit Simulation Framework2020 21st International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED48828.2020.9137047(452-456)Online publication date: Mar-2020
https://doi.org/10.1109/ISQED48828.2020.9137047
Abrishami MPedram MNazarian S(2019)CSM-NN: Current Source Model Based Logic Circuit Simulation - A Neural Network Approach2019 IEEE 37th International Conference on Computer Design (ICCD)10.1109/ICCD46524.2019.00061(393-400)Online publication date: Nov-2019
https://doi.org/10.1109/ICCD46524.2019.00061

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