Article

Free access

Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits

Authors:

Vamsi Boppana,

W. Kent FuchsAuthors Info & Claims

ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

Pages 147 - 154

https://doi.org/10.1145/288548.288593

Published: 01 November 1998 Publication History

PDF eReader

References

[1]

I. Pomeranz and S. M. Reddy, "The multiple observation time test strategy" IEEE Trans. Computer-Aided Design, vol. 40, no. 5, pp. 627-637, May 1992.

Digital Library

Google Scholar

[2]

I. Pomeranz and S. M. Reddy, "Classification of faults in synchronous sequential circuits," IEEE Trans. Computers, vol. 42, no. 9, pp. 1066-1077, Sept. 1993.

Digital Library

Google Scholar

[3]

M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital System Testing and Testable Design, New York, NY: Computer Science Press, 1990.

Google Scholar

[4]

J. Savir and J. P. Roth, 'q'esting for, and distinguishing between failures" in Proc. Intl. Symp. Fault Tolerant Computing, June 1982, pp. 165-I 72.

Google Scholar

[5]

P. Camurati, D. Medina,'P. Prinetto, and M. Sonza Reorda, "A diagnostic test pattern generation algorithm," in Proc. Intl. Test Conf., Sept. 1990, pp. 52-58.

Google Scholar

[6]

T. Griining, U. Mahlstedt, and H. Koopmeiners, "DIATEST: A fast diagnostic test pattern generator for combinational circuits" in Proc. Intl. Conf. Computer-Aided Design, Nov. 1991, pp. 194--197.

Crossref

Google Scholar

[7]

i. Hartanto, V. Boppana, and W. K. Fuchs, "Diagnostic fault equivalence identification using redundancy information & structural analysis" in Proc. Intl. Test Conf., Oct. 1996, pp. 294-302.

Digital Library

Google Scholar

[8]

E. J. McCluskey and E W. Clegg, "Fault equivalence in combinational logic networks,' IEEE Trans. Computers, vol. C-20, no. 1 I, pp. 1286-1293, Nov. 1971.

Google Scholar

[9]

A. Goundan and J. E Hayes, "Identification of equivalent faults in logic networks" IEEE Trans. Computers, vol. C- 29, no. i i, pp. 978-985, Nov. 1980.

Google Scholar

[10]

B. K. Roy, "Diagnosis and fault equivalences in combinational circuits" IEEE Trans. Computers, vol. C-23, no. 9, pp. 955-963, Sept. 1974.

Google Scholar

[11]

A. Lioy, "Advanced fault collapsing" IEEE Design & Test of Computers, vol. 9, no. I, pp. 64-7 I, Mar. 1992.

Digital Library

Google Scholar

[12]

V. Boppana, I. Hartanto, and W. K. Fuchs, "Characterization and implicit identification of sequential indistinguishability" in Proc. Intl. Conf. VLSI Design, Jan. 1997, pp. 376-380.

Digital Library

Google Scholar

[13]

V. Boppana, "State information-based solutions for sequential circuit diagnosis and testing" Ph.D. thesis, Center for Reliable and High-Performance Computing, University of Illinois at Urbana-Champaign, Tech. Rep. CRHC-97-20, July 1997.

Digital Library

Google Scholar

[14]

I. Hartanto, V. Boppana, J. H. Patel, and W. K. Fuchs, "Diagnostic test pattern generation for sequential circuits" in Proc. VLSI Test Symp., Apr. 1997, pp. 196-202.

Digital Library

Google Scholar

[15]

J.E. Chen, C. L. Lee, and W. J. Shen, "Single Fault Fault Collapsing Analysis in Sequential Logic Circuits" IEEE Trans. Computer-Aided Design, vol. 10, no. 10, pp. 1559- 1568, Oct. 1991.

Crossref

Google Scholar

[16]

i. Pomeranz and S. M. Reddy, "On improving fault diagnosis for synchronous sequential circuits" in Proc. Design Automation Conf., June 1994, pp. 504-509.

Digital Library

Google Scholar

[17]

C. Pixley, "A theory and implementation of sequential hardware equivalence" IEEE Trans. Computer-Aided Design, vol. 11, no. 12, pp. 1469-1494, Dec. 1992.

Digital Library

Google Scholar

[18]

S. Y. Huang, K. T. Cheng, K. C. Chert, and U. Glaeser, "An ATPG-based framework for verifying sequential equivalence" in Proc. Intl. Test Conf., Oct. 1996, pp. 865-874.

Digital Library

Google Scholar

[19]

Z. Kohavi, Switching and Finite Automata Theory, New York, NY: McGraw-Hill, 1978.

Digital Library

Google Scholar

[20]

E C. Hennie, Finite-State Models for Logical Machines, New York, NY: John Wiley & Sons, Inc., 1968.

Google Scholar

[21]

T. Niermann and J. H. Patel, "HITEC: A test generation package for sequential circuits" in Proc. European Design Automation Conf., Feb. 1991, pp. 214-218.

Digital Library

Google Scholar

[22]

W.T. Cheng and S. Davidson, "Sequential circuit test generator STG benchmark results,' IEEE Intl. Symp. Circuits and Systems, pp. 1938--1941, May 1989.

Google Scholar

Cited By

View all

Bartenstein T(2000)Fault Distinguishing Pattern GenerationProceedings of the 2000 IEEE International Test Conference10.5555/839295.843540Online publication date: 3-Oct-2000
https://dl.acm.org/doi/10.5555/839295.843540
Amyeen MFuchs WPomeranz IBoppana V(1999)Implication and Evaluation Techniques for Proving Fault EquivalenceProceedings of the 1999 17TH IEEE VLSI Test Symposium10.5555/832299.836503Online publication date: 26-Apr-1999
https://dl.acm.org/doi/10.5555/832299.836503

Index Terms

Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits
1. Hardware

Recommendations

Combinational automatic test pattern generation for acyclic sequential circuits

It is known that the complexity of automatic test pattern generation (ATPG) for acyclic sequential circuits is similar to that of combinational ATPG. The general problem, however, requires time-frame expansion and multiple-fault detection and hence does ...
On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits

We study the relationship between diagnostic test generation for a gate-level fault model, which is used for generating diagnostic test sets for manufacturing defects, and functional test generation for a high-level fault model. In general, a functional ...
Diagnostic Test Pattern Generation for Sequential Circuits
VTS '97: Proceedings of the 15th IEEE VLSI Test Symposium

A method to perform diagnostic test generation in sequential circuits by modifying a conventional test generator is presented. The method utilizes circuit netlist modification along with a forced value at a primary input in the modified circuit. ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

November 1998

704 pages

ISBN:1581130082

DOI:10.1145/288548

Chairman:
Hiroto Yasuura
Kyushu Univ., Fukuoka, Japan

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 November 1998

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

ICCAD '98

Sponsor:

IEEE-EDS
SIGDA
IEEE-CAS
IEEE-CS

ICCAD '98: International Conference on Computer-Aided Design - 1998

November 8 - 12, 1998

California, San Jose, USA

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
229
Total Downloads

Downloads (Last 12 months)35
Downloads (Last 6 weeks)8

Reflects downloads up to 23 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Bartenstein T(2000)Fault Distinguishing Pattern GenerationProceedings of the 2000 IEEE International Test Conference10.5555/839295.843540Online publication date: 3-Oct-2000
https://dl.acm.org/doi/10.5555/839295.843540
Amyeen MFuchs WPomeranz IBoppana V(1999)Implication and Evaluation Techniques for Proving Fault EquivalenceProceedings of the 1999 17TH IEEE VLSI Test Symposium10.5555/832299.836503Online publication date: 26-Apr-1999
https://dl.acm.org/doi/10.5555/832299.836503

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Combinational automatic test pattern generation for acyclic sequential circuits

On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits

Diagnostic Test Pattern Generation for Sequential Circuits