Article

Free access

Development and validation of a hierarchical memory model incorporating CPU- and memory-operation overlap model

Authors:

Kirk W. CameronAuthors Info & Claims

WOSP '98: Proceedings of the 1st international workshop on Software and performance

Pages 152 - 163

https://doi.org/10.1145/287318.287351

Published: 01 October 1998 Publication History

PDF eReader

References

[1]

Wulf, W. A. and McKee, S. A. "Hitting the Memory Wall: Implications of the Obvious," Computer Architecture News, Association for Computing Machinery, March, 1995.

Digital Library

Google Scholar

[2]

Burger, D. C., Goodman, J. R., and Kagi, A., "The Declining Effectiveness of Dynamic Caching for General- Purpose Microprocessors," Univ. Wisconsin Computer Sciences Tech. Report CS-TR-95-1261, Jan. 1995, and references therein.

Google Scholar

[3]

Galles, M. and Williams, E., "Performance Optimizations, Implementation, and Verification of the SG! Challenge Multiprocessor," Silicon Graphics Computer Systems," Silicon Graphics Computer Systems, Mountain View, CA web paper http://w ww. sg i. com/T echno 1 o gy/c hal 1 en ge___pap er. h t m 1.

Google Scholar

[4]

Laudon, J. and Lenowski, D., "The SGI Origin: A ccNUMA Highly Scalable Server," Proc. Compcon Spring. 1997, IEEE Computer Society, Los Alamitos, California.

Google Scholar

[5]

MIPS Technologies, Inc., "R10000 Microprocessor Product Overview," MIPS Product Preview, I995. (b) Yeager, K. C., "The MIPS R10000 Superscalar Microprocessor," IEEE Micro, April, 1996, pp 28-40.

Digital Library

Google Scholar

[6]

Zagha, M., Larson, B., Turner, S., and Itzkowitz, M., "Performance Analysis Using the MIPS R IO000 Performance Counters," Proc. Supercomputing '96, IEEE Computer Society, Los Alamitos, California, 1996.

Digital Library

Google Scholar

[7]

Luo, Y., Lubeck, O.M., and Wasserman, H. J., "Preliminary Performance Study of the SGI Origin2000," Los Alamos National Laboratory Unclassified Release LA- UR -, 1997.

Google Scholar

[8]

Koch, K. R., Baker, R. S. and Alcouffe, R. E., "Solution of the First-Order Form of the 3-D Discrete Ordinates Equation on a Massively Parallel Processor," Trans. of the Amer. Nuc. Soc., 65, 198, 1992.

Google Scholar

[9]

W.D. Schulz, "Two-Dimensional Lagrangian Hydrodynamic Difference Equations," Methods in Computational Phys. Vol 3, p l, 1964.

Google Scholar

[10]

McVoy, L. and Staelin, C., "lmbench: Portable Tools for Performance Analysis," http ://real i ty. sgi. c om/lm_engr/lm bench.

Google Scholar

[11]

Vernon, M.V, Lazowska, E. D., and Zahorjan, J., "An Accurate and Efficient Performance Analysis Technique for Multiprocessor Snooping Cache-consistency Protocols," in Proc. 15th Annu. Syrup. Comput. Architecture, Honolulu, HI, June, 1988, pp 308-315.

Digital Library

Google Scholar

[12]

Larson, B., Silicon Graphics Computer Systems, private communication, January, 1997.

Google Scholar

[13]

Turner, S., Silicon Graphics Computer Systems, private communication, January, 1997.

Google Scholar

[14]

Bhandarkar, D. and Cvetanovic, Z., "Performance Characterization of the Alpha 21164 Microprocessor Using TP and SPEC Workloads," Proc. Second. Int. Sypm. on High-Perf. Comp. Arch., IEEE Computer Society Press, Los Alamitos Ca., 1996.

Digital Library

Google Scholar

[15]

Bhandarkar, D. and Ding, J., "Performance Characterization of the Pentium Pro Processor, " Proc. Third. Int. Sypm. on High-Perf. Comp. Arch., IEEE Computer Society Press, Los Alamitos Ca., pp 288-297, 1997.

Crossref

Google Scholar

[16]

Mattson, T. and Henry, G., "An Overview of the lntel TLFOPS Supercomputer", Intel Technical Journal, Jan. 1998.

Google Scholar

[17]

Sandia National Lab, "The ASCI Red TFLOPS Supercomputer", http://www'sandia'g~v/ASCI/Red/ Nov. 1996.

Google Scholar

Cited By

View all

Zhou MDu YChilders BMosse DMelhem R(2016)Symmetry-Agnostic Coordinated Management of the Memory Hierarchy in Multicore SystemsACM Transactions on Architecture and Code Optimization10.1145/284725412:4(1-26)Online publication date: 4-Jan-2016
https://dl.acm.org/doi/10.1145/2847254
Zhou MDu YChilders BMelhem RMosse DFensch CO'Boyle MSeznec ABodin F(2013)Writeback-aware bandwidth partitioning for multi-core systems with PCMProceedings of the 22nd international conference on Parallel architectures and compilation techniques10.5555/2523721.2523740(113-122)Online publication date: 7-Oct-2013
https://dl.acm.org/doi/10.5555/2523721.2523740
Miao Zhou Yu Du Childers BMelhem RMosse D(2013)Writeback-aware bandwidth partitioning for multi-core systems with PCMProceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT.2013.6618809(113-122)Online publication date: Sep-2013
https://doi.org/10.1109/PACT.2013.6618809
Show More Cited By

Index Terms

Development and validation of a hierarchical memory model incorporating CPU- and memory-operation overlap model

Recommendations

Efficient memory management of a hierarchical and a hybrid main memory for MN-MATE platform
PMAM '12: Proceedings of the 2012 International Workshop on Programming Models and Applications for Multicores and Manycores

The advent of manycore in computing architecture causes severe energy consumption and memory wall problem. Thus, emerging technologies such as on-chip memory and nonvolatile memory (NVRAM) have led to a paradigm shift in computing architecture era. For ...
Write-once-memory-code phase change memory
DATE '14: Proceedings of the conference on Design, Automation & Test in Europe

This paper describes a write-once-memory-code phase change memory (WOM-code PCM) architecture for next-generation non-volatile memory applications. Specifically, we address the long latency of the write operation in PCM --- attributed to PCM SET --- by ...
Enabling Hybrid PCM Memory System with Inherent Memory Management
RACS '16: Proceedings of the International Conference on Research in Adaptive and Convergent Systems

Replacing the traditional volatile main memory, e.g., DRAM, with a non-volatile phase change memory (PCM) has become a possible solution to reduce the energy consumption of computing systems. To further reduce the bit cost of PCM, the development trend ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

WOSP '98: Proceedings of the 1st international workshop on Software and performance

October 1998

232 pages

ISBN:1581130600

DOI:10.1145/287318

Chairmen:
Connie U. Smith
Performance Engineering Services, Santa Fe, NM
,
Paul Clements
Carnegie Mellon Univ., Pittsburgh, PA
,
Murray Woodside
Carleton Univ., Ottawa, Ont., Canada

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 October 1998

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

WOSP98

Sponsor:

WOSP98: 1998 Workshop on Software and Performance

October 12 - 16, 1998

New Mexico, Santa Fe, USA

Acceptance Rates

WOSP '98 Paper Acceptance Rate 27 of 44 submissions, 61%;

Overall Acceptance Rate 149 of 241 submissions, 62%

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

10
Total Citations
View Citations
397
Total Downloads

Downloads (Last 12 months)67
Downloads (Last 6 weeks)10

Reflects downloads up to 14 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Zhou MDu YChilders BMosse DMelhem R(2016)Symmetry-Agnostic Coordinated Management of the Memory Hierarchy in Multicore SystemsACM Transactions on Architecture and Code Optimization10.1145/284725412:4(1-26)Online publication date: 4-Jan-2016
https://dl.acm.org/doi/10.1145/2847254
Zhou MDu YChilders BMelhem RMosse DFensch CO'Boyle MSeznec ABodin F(2013)Writeback-aware bandwidth partitioning for multi-core systems with PCMProceedings of the 22nd international conference on Parallel architectures and compilation techniques10.5555/2523721.2523740(113-122)Online publication date: 7-Oct-2013
https://dl.acm.org/doi/10.5555/2523721.2523740
Miao Zhou Yu Du Childers BMelhem RMosse D(2013)Writeback-aware bandwidth partitioning for multi-core systems with PCMProceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT.2013.6618809(113-122)Online publication date: Sep-2013
https://doi.org/10.1109/PACT.2013.6618809
Guo FSolihin YZhao LIyer R(2010)Quality of service shared cache management in chip multiprocessor architectureACM Transactions on Architecture and Code Optimization10.1145/1880037.18800397:3(1-33)Online publication date: 30-Dec-2010
https://dl.acm.org/doi/10.1145/1880037.1880039
Fang Liu Xiaowei Jiang Yan Solihin (2010)Understanding how off-chip memory bandwidth partitioning in Chip Multiprocessors affects system performanceHPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture10.1109/HPCA.2010.5416655(1-12)Online publication date: Jan-2010
https://doi.org/10.1109/HPCA.2010.5416655
Ottoni GAugust D(2007)Global Multi-Threaded Instruction SchedulingProceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2007.17(56-68)Online publication date: 1-Dec-2007
https://dl.acm.org/doi/10.1109/MICRO.2007.17
Srinivasan RLubeck O(2005)MonteSimACM SIGARCH Computer Architecture News10.1145/1127577.112759233:5(75-80)Online publication date: 1-Dec-2005
https://dl.acm.org/doi/10.1145/1127577.1127592
Carrington LLaurenzano MSnavely ACampbell RDavis LKramer W(2005)How Well Can Simple Metrics Represent the Performance of HPC Applications?Proceedings of the 2005 ACM/IEEE conference on Supercomputing10.1109/SC.2005.33Online publication date: 12-Nov-2005
https://dl.acm.org/doi/10.1109/SC.2005.33
Sun XCameron K(2000)A Statistical-Empirical Hybrid Approach to Hierarchical Memory AnalysisEuro-Par 2000 Parallel Processing10.1007/3-540-44520-X_18(141-148)Online publication date: 18-Aug-2000
https://doi.org/10.1007/3-540-44520-X_18
Yong Luo Cameron K(1999)Instruction-level characterization of scientific computing applications using hardware performance countersWorkload Characterization: Methodology and Case Studies. Based on the First Workshop on Workload Characterization10.1109/WWC.1998.809368(125-131)Online publication date: 1999
https://doi.org/10.1109/WWC.1998.809368

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Efficient memory management of a hierarchical and a hybrid main memory for MN-MATE platform

Write-once-memory-code phase change memory

Enabling Hybrid PCM Memory System with Inherent Memory Management