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SDSoC: A Higher-level Programming Environment for Zynq SoC and Ultrascale+ MPSoC

Published: 21 February 2016 Publication History

Abstract

Zynq-7000 All Programmable SoC and the new Zynq Ultrascale+ MPSoC provide proven alternatives to traditional domain-specific application SoCs and enable extensive system-level differentiation, integration and flexibility through hardware, software and I/O programmability.
The SDSoC Development Environment is a heterogeneous design environment for implementing embedded systems using the Zynq SoC and MPSoC. It enables the broader community of embedded software developers to leverage the power of hardware and software programmable devices, entirely from a higher-level of abstraction.
The SDSoC environment provides a greatly simplified embedded C/C++ application programming experience including an easy-to-use Eclipse IDE and a comprehensive development platform. SDSoC includes a full-system optimizing C/C++ compiler, system-level profiling and hardware/software event tracing, automated software acceleration in programming logic, automated generation of SW-HW connectivity, and integration with libraries to speed programing. The SDSoC compiler transforms programs into complete hardware/software systems based on user-specified target platform and functions within the program to compile into programmable hardware logic. Hardware accelerators communicate with the CPU and external memory through an automatically-generated, application-specific data motion network comprised of DMAs, interconnects and other standard IP blocks.
The SDSoC Environment also provides flows for customer and 3rd party developers to enable their platforms and integrate RTL IPs as C-callable libraries. It builds upon customer-proven design tools from Xilinx including Vivado Design Suite, Vivado High-level Synthesis and SDK.
In this presentation, we will introduce the motivation and basic concepts behind SDSoC, describe its capabilities and the user-flow, and provide a brief demonstration of the tool using an example.

Cited By

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  • (2023)SqueezeJet-3: An HLS-based Accelerator for Edge CNN Applications on SoC FPGAs2023 XXIX International Conference on Information, Communication and Automation Technologies (ICAT)10.1109/ICAT57854.2023.10171329(1-6)Online publication date: 11-Jun-2023
  • (2023)Securator: A Fast and Secure Neural Processing Unit2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071091(1127-1139)Online publication date: Feb-2023
  • (2022)A Soft Coprocessor Approach for Developing Image and Video Processing Applications on FPGAsJournal of Imaging10.3390/jimaging80200428:2(42)Online publication date: 11-Feb-2022
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Published In

cover image ACM Conferences
FPGA '16: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
February 2016
298 pages
ISBN:9781450338561
DOI:10.1145/2847263
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 21 February 2016

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Author Tags

  1. heterogeneous architecture exploration
  2. heterogeneous programming
  3. high-level synthesis
  4. higher-level programming for cpu and fpga systems
  5. sdsoc
  6. software-defined systems-on-chip
  7. sw-hw connectivity
  8. sw-hw design exploration
  9. zynq and zynq ultrascale+ mpsoc programming environment

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FPGA '16 Paper Acceptance Rate 20 of 111 submissions, 18%;
Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

View all
  • (2023)SqueezeJet-3: An HLS-based Accelerator for Edge CNN Applications on SoC FPGAs2023 XXIX International Conference on Information, Communication and Automation Technologies (ICAT)10.1109/ICAT57854.2023.10171329(1-6)Online publication date: 11-Jun-2023
  • (2023)Securator: A Fast and Secure Neural Processing Unit2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071091(1127-1139)Online publication date: Feb-2023
  • (2022)A Soft Coprocessor Approach for Developing Image and Video Processing Applications on FPGAsJournal of Imaging10.3390/jimaging80200428:2(42)Online publication date: 11-Feb-2022
  • (2022)HFOD: A hardware-friendly quantization method for object detection on embedded FPGAsIEICE Electronics Express10.1587/elex.19.2022006719:8(20220067-20220067)Online publication date: 25-Apr-2022
  • (2022)Continual Learning With Speculative Backpropagation and Activation HistoryIEEE Access10.1109/ACCESS.2022.316615810(38555-38564)Online publication date: 2022
  • (2021)A Customized Floating-point Processor Design for FPGA and ASIC based Thermal Compensation in High-precision SensingAnnals of Emerging Technologies in Computing10.33166/AETiC.2021.01.0045:1(40-50)Online publication date: 1-Jan-2021
  • (2021)Inf4Edge: Automatic Resource-aware Generation of Energy-efficient CNN Inference Accelerator for Edge Embedded FPGAs2021 12th International Green and Sustainable Computing Conference (IGSC)10.1109/IGSC54211.2021.9651650(1-8)Online publication date: 18-Oct-2021
  • (2021)Application and Exploration of Artificial Intelligence and Edge Computing in Long-Distance Education on Mobile NetworkMobile Networks and Applications10.1007/s11036-021-01773-x26:5(2164-2175)Online publication date: 1-May-2021
  • (2020)Design of Medical Image Hardware Acceleration Platform by SDSoC for ZYNQ SoCJournal of Image and Graphics10.18178/joig.8.4.98-1068:4(98-106)Online publication date: 2020
  • (2020)DeepHLS: A complete toolchain for automatic synthesis of deep neural networks to FPGA2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)10.1109/ICECS49266.2020.9294881(1-4)Online publication date: 23-Nov-2020
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