research-article

The Stratix™ 10 Highly Pipelined FPGA Architecture

Authors:

Jeffrey Chromczak,

David Galloway,

Valavan Manohararajah,

Tim Vanderhoek,

John Van DykenAuthors Info & Claims

FPGA '16: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Pages 159 - 168

https://doi.org/10.1145/2847263.2847267

Published: 21 February 2016 Publication History

Abstract

This paper describes architectural enhancements in the Altera Stratix? 10 HyperFlex? FPGA architecture, fabricated in the Intel 14nm FinFET process. Stratix 10 includes ubiquitous flip-flops in the routing to enable a high degree of pipelining. In contrast to the earlier architectural exploration of pipelining in pass-transistor based architectures, the direct drive routing fabric in Stratix-style FPGAs enables an extremely low-cost pipeline register. The presence of ubiquitous flip-flops simplifies circuit retiming and improves performance. The availability of predictable retiming affects all stages of the cluster, place and route flow. Ubiquitous flip-flops require a low-cost clock network with sufficient flexibility to enable pipelining of dozens of clock domains. Different cost/performance tradeoffs in a pipelined fabric and use of a 14nm process, lead to other modifications to the routing fabric and the logic element. User modification of the design enables even higher performance, averaging 2.3X faster in a small set of designs.

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Cited By

Nandi PMishra ARao M(2024)GOLDS: Genetic Algorithm-based Optimization of Custom FPGA Architecture Layout Design for Secure SiliconProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658743(92-97)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658743
Hassani FSadrosadati MRohbani NPointner SWille RSarbazi-azad H(2024)An Efficient FPGA Architecture with Turn-Restricted Switch BoxesACM Transactions on Design Automation of Electronic Systems10.1145/3643809Online publication date: 3-Feb-2024
https://doi.org/10.1145/3643809
Shi KWang L(2024)An Open-Source Tool to Model and Explore Complex Routing Architecture for FPGA2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617494(734-739)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617494
Show More Cited By

Index Terms

The Stratix™ 10 Highly Pipelined FPGA Architecture
1. Hardware
  1. Integrated circuits
    1. Reconfigurable logic and FPGAs
      1. Programmable interconnect
      2. Programmable logic elements

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Published In

cover image ACM Conferences

FPGA '16: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 2016

298 pages

ISBN:9781450338561

DOI:10.1145/2847263

General Chair:
Deming Chen
University of Illinois at Urbana-Champaign, USA
,
Program Chair:
Jonathan Greene
Microsemi, USA

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Published: 21 February 2016

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FPGA'16

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SIGDA

FPGA'16: The 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 21 - 23, 2016

California, Monterey, USA

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FPGA '16 Paper Acceptance Rate 20 of 111 submissions, 18%;

Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

Nandi PMishra ARao M(2024)GOLDS: Genetic Algorithm-based Optimization of Custom FPGA Architecture Layout Design for Secure SiliconProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658743(92-97)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658743
Hassani FSadrosadati MRohbani NPointner SWille RSarbazi-azad H(2024)An Efficient FPGA Architecture with Turn-Restricted Switch BoxesACM Transactions on Design Automation of Electronic Systems10.1145/3643809Online publication date: 3-Feb-2024
https://doi.org/10.1145/3643809
Shi KWang L(2024)An Open-Source Tool to Model and Explore Complex Routing Architecture for FPGA2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617494(734-739)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617494
Doumet MStan MHall MBetz V(2024)H2PIPE: High Throughput CNN Inference on FPGAs with High-Bandwidth Memory2024 34th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL64840.2024.00019(69-77)Online publication date: 2-Sep-2024
https://doi.org/10.1109/FPL64840.2024.00019
Sano KKoshiba AMiyajima TUeno T(2023)ESSPER: Elastic and Scalable FPGA-Cluster System for High-Performance Reconfigurable Computing with Supercomputer FugakuProceedings of the International Conference on High Performance Computing in Asia-Pacific Region10.1145/3578178.3579341(140-150)Online publication date: 27-Feb-2023
https://dl.acm.org/doi/10.1145/3578178.3579341
Shi KZhou HWang L(2023)Explore the Feedback Interconnects in Intra-Cluster Routing for FPGAs2023 International Conference on Field Programmable Technology (ICFPT)10.1109/ICFPT59805.2023.00034(250-253)Online publication date: 12-Dec-2023
https://doi.org/10.1109/ICFPT59805.2023.00034
Khoozani KDehkordi ABetz V(2023)Titan 2.0: Enabling Open-Source CAD Evaluation with a Modern Architecture Capture2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL60245.2023.00016(57-64)Online publication date: 4-Sep-2023
https://doi.org/10.1109/FPL60245.2023.00016
Zhang JZhu KShi KWang LZhou H(2023)Efficient FPGA Routing Architecture Exploration Based on Two-Stage MUXes2023 IEEE 15th International Conference on ASIC (ASICON)10.1109/ASICON58565.2023.10395964(1-4)Online publication date: 24-Oct-2023
https://doi.org/10.1109/ASICON58565.2023.10395964
Boutros ABetz V(2023)Field-Programmable Gate Array ArchitectureHandbook of Computer Architecture10.1007/978-981-15-6401-7_49-1(1-47)Online publication date: 7-Jan-2023
https://doi.org/10.1007/978-981-15-6401-7_49-1
Shi KZhou XZhou HWang L(2022)An Optimized GIB Routing Architecture with Bent Wires for FPGAACM Transactions on Reconfigurable Technology and Systems10.1145/351959916:1(1-28)Online publication date: 22-Dec-2022
https://dl.acm.org/doi/10.1145/3519599
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