Fabrics on Die: Where Function, Debug and Test Meet

The typical multi core SOC of today faces several development constraints. While the process and methodology plans for a first pass silicon, it is not always guaranteed. A true SOC design team always plans for debug capability when the SOC samples ...

NOC architectures have to deliver good latency-throughput performance in the face of very tight power and area budgets. However, the latency and the power consumption for transferring information down the transmitter stack, through the channel, and up ...

The increasing test-data volumes needed for the testing of system-on-chip (SOC) integrated circuits lead to long test-application times and high tester memory requirements. Efficient test planning and test-data compression are therefore needed. We ...