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Parallel real-time garbage collection of multiple heaps in reconfigurable hardware

Published: 12 June 2014 Publication History

Abstract

Despite rapid increases in memory capacity, reconfigurable hardware is still programmed in a very low-level manner, generally without any dynamic allocation at all. This limits productivity especially as the larger chips encourage more and more complex designs to be attempted.
Prior work has shown that it is possible to implement a real-time collector in hardware and achieve stall-free operation --- but at the price of severe restrictions on object layouts. We present the first hardware garbage collector capable of collecting multiple inter-connected heaps, thereby allowing a rich set of object types.
We show that for a modest additional cost in logic and memory, we can support multiple heaps at a clock frequency competitive with monolithic, fixed-layout heaps. We evaluate the hardware design by synthesizing it for a Xilinx FPGA and using co-simulation to measure the run-time behavior over a set of four benchmarks. Even at high allocation and mutation rates the collector is able to sustain stall-free (100% minimum mutator utilization) operation with up to 4 inter-connected heaps, while only requiring between 1.1 and 1.7 times the maximum live memory of the application.

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Cited By

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  • (2022)Synthesized In-BramGarbage Collection for Accelerators with Immutable Memory2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL57034.2022.00019(47-53)Online publication date: Aug-2022
  • (2018)Transactional SapphireACM Transactions on Programming Languages and Systems10.1145/322622540:4(1-56)Online publication date: 10-Dec-2018
  • (2015)Don't race the memory bus: taming the GC leadfootACM SIGPLAN Notices10.1145/2887746.275418250:11(15-27)Online publication date: 14-Jun-2015
  • Show More Cited By

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    Published In

    cover image ACM SIGPLAN Notices
    ACM SIGPLAN Notices  Volume 49, Issue 11
    ISMM '14
    November 2014
    121 pages
    ISSN:0362-1340
    EISSN:1558-1160
    DOI:10.1145/2775049
    • Editor:
    • Andy Gill
    Issue’s Table of Contents
    • cover image ACM Conferences
      ISMM '14: Proceedings of the 2014 international symposium on Memory management
      June 2014
      136 pages
      ISBN:9781450329217
      DOI:10.1145/2602988
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 12 June 2014
    Published in SIGPLAN Volume 49, Issue 11

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    Author Tags

    1. block ram
    2. fpga
    3. garbage collection
    4. high level synthesis
    5. real time

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    Cited By

    View all
    • (2022)Synthesized In-BramGarbage Collection for Accelerators with Immutable Memory2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL57034.2022.00019(47-53)Online publication date: Aug-2022
    • (2018)Transactional SapphireACM Transactions on Programming Languages and Systems10.1145/322622540:4(1-56)Online publication date: 10-Dec-2018
    • (2015)Don't race the memory bus: taming the GC leadfootACM SIGPLAN Notices10.1145/2887746.275418250:11(15-27)Online publication date: 14-Jun-2015
    • (2015)Don't race the memory bus: taming the GC leadfootProceedings of the 2015 International Symposium on Memory Management10.1145/2754169.2754182(15-27)Online publication date: 14-Jun-2015
    • (2018)Transactional SapphireACM Transactions on Programming Languages and Systems10.1145/322622540:4(1-56)Online publication date: 10-Dec-2018
    • (2017)From functional programs to pipelined dataflow circuitsProceedings of the 26th International Conference on Compiler Construction10.1145/3033019.3033027(76-86)Online publication date: 5-Feb-2017
    • (2015)Don't race the memory bus: taming the GC leadfootACM SIGPLAN Notices10.1145/2887746.275418250:11(15-27)Online publication date: 14-Jun-2015
    • (2015)Don't race the memory bus: taming the GC leadfootProceedings of the 2015 International Symposium on Memory Management10.1145/2754169.2754182(15-27)Online publication date: 14-Jun-2015

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