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Design methodologies for noise in digital integrated circuits

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Kenneth L. ShepardAuthors Info & Claims

DAC '98: Proceedings of the 35th annual Design Automation Conference

Pages 94 - 99

https://doi.org/10.1145/277044.277062

Published: 01 May 1998 Publication History

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Abstract

In this paper, we describe the growing problems of noise in digital integrated circuits and the design tools and techniques used to ensure the noise immunity of digital designs.

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Jha BGupta KPandey R(2022)Low Voltage Schmitt Trigger Full Adders Design for High Noise Immunity2022 8th International Conference on Signal Processing and Communication (ICSC)10.1109/ICSC56524.2022.10009098(618-623)Online publication date: 1-Dec-2022
https://doi.org/10.1109/ICSC56524.2022.10009098
Nayini SSai Kushal Gella KDubey SGuduri MIslam A(2021)Robust Design of Noise Tolerant 2-Phase Non Overlapping Clock Generating Circuit2021 Devices for Integrated Circuit (DevIC)10.1109/DevIC50843.2021.9455843(211-215)Online publication date: 19-May-2021
https://doi.org/10.1109/DevIC50843.2021.9455843
Rao SReddy N(2017)An energy efficient improved RPL routing protocol2017 International Conference on Intelligent Computing and Control (I2C2)10.1109/I2C2.2017.8321954(1-7)Online publication date: Jun-2017
https://doi.org/10.1109/I2C2.2017.8321954
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Design methodologies for noise in digital integrated circuits

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Published In

DAC '98: Proceedings of the 35th annual Design Automation Conference

May 1998

820 pages

ISBN:0897919645

DOI:10.1145/277044

Chairmen:
Basant R. Chawla
Lucent Technologies, Warren, NJ
,
Randal E. Bryant
Carnegie Mellon Univ., Pittsburgh, PA
,
Jan M. Rabaey
Univ. of California, Berkeley
,
Editor:
M. J. Irwin

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1998

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DAC98: The 35th ACM/IEEE-CAS/EDAC Design Automation Conference

June 15 - 19, 1998

California, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Jha BGupta KPandey R(2022)Low Voltage Schmitt Trigger Full Adders Design for High Noise Immunity2022 8th International Conference on Signal Processing and Communication (ICSC)10.1109/ICSC56524.2022.10009098(618-623)Online publication date: 1-Dec-2022
https://doi.org/10.1109/ICSC56524.2022.10009098
Nayini SSai Kushal Gella KDubey SGuduri MIslam A(2021)Robust Design of Noise Tolerant 2-Phase Non Overlapping Clock Generating Circuit2021 Devices for Integrated Circuit (DevIC)10.1109/DevIC50843.2021.9455843(211-215)Online publication date: 19-May-2021
https://doi.org/10.1109/DevIC50843.2021.9455843
Rao SReddy N(2017)An energy efficient improved RPL routing protocol2017 International Conference on Intelligent Computing and Control (I2C2)10.1109/I2C2.2017.8321954(1-7)Online publication date: Jun-2017
https://doi.org/10.1109/I2C2.2017.8321954
Rao PObulesu B(2017)A low power low area crosstalk avoidance logic for 45nm ASIC applications2017 International Conference on Intelligent Computing and Control (I2C2)10.1109/I2C2.2017.8321826(1-7)Online publication date: Jun-2017
https://doi.org/10.1109/I2C2.2017.8321826
Gavrilov SIvanova GRyzhova DVolobuev P(2016)Multi-interval static timing analysis accounting logic compatibility2016 IEEE East-West Design & Test Symposium (EWDTS)10.1109/EWDTS.2016.7807650(1-4)Online publication date: Oct-2016
https://doi.org/10.1109/EWDTS.2016.7807650
Kim KKim S(2015)Design of Schmitt Trigger Logic Gates Using DTMOS for Enhanced Electromagnetic Immunity of Subthreshold CircuitsIEEE Transactions on Electromagnetic Compatibility10.1109/TEMC.2015.242799257:5(963-972)Online publication date: Oct-2015
https://doi.org/10.1109/TEMC.2015.2427992
Bhukya RRout B(2015)An effective design of high performance dynamic feed through logic and noise tolerance circuitsInternational Conference on Computing, Communication & Automation10.1109/CCAA.2015.7148587(1349-1352)Online publication date: May-2015
https://doi.org/10.1109/CCAA.2015.7148587
Wey IChang CLiao YChou H(2014)Noise‐tolerant dynamic CMOS circuits design by using true single‐phase clock latching techniqueInternational Journal of Circuit Theory and Applications10.1002/cta.197643:7(854-865)Online publication date: 10-Jan-2014
https://doi.org/10.1002/cta.1976
KyungSoo Kim Wansoo Nah SoYoung Kim (2013)Noise-immune design of Schmitt trigger logic gate using DTMOS for sub-threshold circuits2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)10.1109/EMCCompo.2013.6735178(83-88)Online publication date: Dec-2013
https://doi.org/10.1109/EMCCompo.2013.6735178
Sahoo SMahapatra K(2012)Noise tolerant circuit techniques for high performance feedthrough logic2012 International Conference on Emerging Trends in Science, Engineering and Technology (INCOSET)10.1109/INCOSET.2012.6513932(354-358)Online publication date: Dec-2012
https://doi.org/10.1109/INCOSET.2012.6513932
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