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A new retiming-based technology mapping algorithm for LUT-based FPGAs

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Chih-Chang LinAuthors Info & Claims

FPGA '98: Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays

Pages 35 - 42

https://doi.org/10.1145/275107.275118

Published: 01 March 1998 Publication History

Abstract

In this paper, w e presen t a new retiming-based technology mapping algorithm for look-up table-based field programmable gate arrays. The algorithm is based on a novel iterative procedure for computing all k-cuts of all nodes in a sequen tialcircuit, in the presence of retiming. The algorithm completely avoids flow computation whic his the bottleneck of previous algorithms. Due to the fact that k is very small in practice, the procedure for computing all k-cuts is v ery fast. Experimental results indicate the overall algorithm is very efficient in practice.

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Cited By

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A new retiming-based technology mapping algorithm for LUT-based FPGAs

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Published In

cover image ACM Conferences

FPGA '98: Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays

March 1998

262 pages

ISBN:0897919785

DOI:10.1145/275107

Chairmen:
Jason Cong
Univ. of California, Los Angeles
,
Sinan Kaptanoglu
Actel Corp.

Copyright © 1998 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 March 1998

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FPGA98

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SIGDA

FPGA98: 1998 International Symposium on Field Programmable Gate Arrays

February 22 - 25, 1998

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

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https://doi.org/10.1109/TCAD.2024.3434464
Li ZYang LLou M(2024)DAGNN-RE: Directed Acyclic Graph Neural Network for Functional Reverse Engineering of Gate-Level NetlistIntegration10.1016/j.vlsi.2024.102343(102343)Online publication date: Dec-2024
https://doi.org/10.1016/j.vlsi.2024.102343
Konrad AScholl CMahzoon AGroße DDrechsler R(2024)Divider verification using symbolic computer algebra and delayed don’t care optimization: theory and practical implementationFormal Methods in System Design10.1007/s10703-024-00452-3Online publication date: 24-May-2024
https://doi.org/10.1007/s10703-024-00452-3
Barzen BReais-Parsi AHung EKang MMishchenko AGreene JWawrzynek J(2023)Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137310(1-6)Online publication date: Apr-2023
https://doi.org/10.23919/DATE56975.2023.10137310
GE XKIMURA S(2023)Theory and Application of Topology-Based Exact Synthesis for Majority-Inverter GraphsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.2022EAP1103E106.A:9(1241-1250)Online publication date: 1-Sep-2023
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Calvino ADe Micheli G(2023)Technology Mapping Using Multi-Output Library Cells2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323999(1-9)Online publication date: 28-Oct-2023
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Wang HRizzi CJosipović L(2023)MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323639(1-9)Online publication date: 28-Oct-2023
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Mahzoon AGroße DDrechsler RMahzoon AGroße DDrechsler R(2023)BackgroundFormal Verification of Structurally Complex Multipliers10.1007/978-3-031-24571-8_2(9-28)Online publication date: 15-Feb-2023
https://doi.org/10.1007/978-3-031-24571-8_2
Mahzoon AGroBe DDrechsler R(2022)RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing RemovalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.308368241:5(1573-1586)Online publication date: May-2022
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