research-article

A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction

Authors:

Andrew B. Kahng,

Siddhartha Nath,

Jongpil LeeAuthors Info & Claims

DAC '15: Proceedings of the 52nd Annual Design Automation Conference

Article No.: 26, Pages 1 - 6

https://doi.org/10.1145/2744769.2744776

Published: 07 June 2015 Publication History

Abstract

As combinations of signoff corners grow in modern SoCs, minimization of clock skew variation across corners is important. Large skew variation can cause difficulties in multi-corner timing closure because fixing violations at one corner can lead to violations at other corners. Such "ping-pong" effects lead to significant power and area overheads and time to signoff. We propose a novel framework encompassing both global and local clock network optimizations to minimize the sum of skew variations across different PVT corners between all sequentially adjacent sink pairs. The global optimization uses linear programming to guide buffer insertion, buffer removal and routing detours. The local optimization is based on machine learning-based predictors of latency change; these are used for iterative optimization with tree surgery, buffer sizing and buffer displacement operators. Our optimization achieves up to 22% total skew variation reduction across multiple testcases implemented in foundry 28nm technology, as compared to a best-practices CTS solution using a leading commercial tool.

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Cited By

Wagle AYang JKulkarni NVrudhula S(2023)A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local ClockingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.326479842:11(4164-4176)Online publication date: Nov-2023
https://doi.org/10.1109/TCAD.2023.3264798
Hu JKahng A(2023)Invited Paper: The Inevitability of AI Infusion Into Design Closure and Signoff2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323684(1-7)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323684
Melikyan VMelikyan V(2023)Design of Digital Integrated Circuits by Improving the Characteristics of Digital CellsMachine Learning-based Design and Optimization of High-Speed Circuits10.1007/978-3-031-50714-4_6(279-336)Online publication date: 31-Dec-2023
https://doi.org/10.1007/978-3-031-50714-4_6
Show More Cited By

Index Terms

A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

cover image ACM Conferences

DAC '15: Proceedings of the 52nd Annual Design Automation Conference

June 2015

1204 pages

ISBN:9781450335201

DOI:10.1145/2744769

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 June 2015

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optimization

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DAC '15

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DAC '15: The 52nd Annual Design Automation Conference 2015

June 7 - 11, 2015

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Wagle AYang JKulkarni NVrudhula S(2023)A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local ClockingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.326479842:11(4164-4176)Online publication date: Nov-2023
https://doi.org/10.1109/TCAD.2023.3264798
Hu JKahng A(2023)Invited Paper: The Inevitability of AI Infusion Into Design Closure and Signoff2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323684(1-7)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323684
Melikyan VMelikyan V(2023)Design of Digital Integrated Circuits by Improving the Characteristics of Digital CellsMachine Learning-based Design and Optimization of High-Speed Circuits10.1007/978-3-031-50714-4_6(279-336)Online publication date: 31-Dec-2023
https://doi.org/10.1007/978-3-031-50714-4_6
Madhuri GSelvakumar JKrishna K(2022)Performance Analysis on Skew Optimized Clock Tree Synthesis2022 Fourth International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT)10.1109/ICERECT56837.2022.10059632(01-06)Online publication date: 26-Dec-2022
https://doi.org/10.1109/ICERECT56837.2022.10059632
Teh EZawawi MMohamed MIsa N(2021)Practical Full Chip Clock Distribution Design With a Flexible Topology and Hybrid Metaheuristic TechniqueIEEE Access10.1109/ACCESS.2021.30530529(14816-14835)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3053052
Han KKahng ALi J(2020)Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock DistributionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288975639:2(478-491)Online publication date: Feb-2020
https://doi.org/10.1109/TCAD.2018.2889756
Chou CHsiao YChang S(2019)Clock Skew Optimization for Voltage Variation2019 China Semiconductor Technology International Conference (CSTIC)10.1109/CSTIC.2019.8755674(1-3)Online publication date: Mar-2019
https://doi.org/10.1109/CSTIC.2019.8755674
Lee JPackeer Mohamed MMd. Zawawi MHashim N(2019)Place and Route Optimization for High Coverage Multi-corner Multi-mode Timing Fix10th International Conference on Robotics, Vision, Signal Processing and Power Applications10.1007/978-981-13-6447-1_25(195-201)Online publication date: 2-Apr-2019
https://doi.org/10.1007/978-981-13-6447-1_25
Uysal NEwetz RShin Y(2018)OCV guided clock tree topology reconstructionProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201726(494-499)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.5555/3201607.3201726
Kahng AShin Y(2018)New directions for learning-based IC design tools and methodologiesProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201708(405-410)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.5555/3201607.3201708
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