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Formalized methodology for data reuse exploration in hierarchical memory mappings

Authors:

J. Ph. Diguet,

S. Wuytack,

F. Catthoor,

H. De ManAuthors Info & Claims

ISLPED '97: Proceedings of the 1997 international symposium on Low power electronics and design

Pages 30 - 35

https://doi.org/10.1145/263272.263278

Published: 01 August 1997 Publication History

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Kritikakou ACatthoor FKelefouras VGoutis C(2014)A scalable and near-optimal representation of access schemes for memory managementACM Transactions on Architecture and Code Optimization10.1145/257967711:1(1-25)Online publication date: 1-Feb-2014
https://dl.acm.org/doi/10.1145/2579677
Hayashizaki HSugawara YInaba MHiraki KMoshovos ATarditi DOlukotun K(2008)MCAMPProceedings of the 17th international conference on Parallel architectures and compilation techniques10.1145/1454115.1454132(102-111)Online publication date: 25-Oct-2008
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Information & Contributors

Information

Published In

ISLPED '97: Proceedings of the 1997 international symposium on Low power electronics and design

August 1997

335 pages

ISBN:0897919033

DOI:10.1145/263272

Chairmen:
Brock Barton
Texas Instruments
,
Massoud Pedram
USC
,
Anantha Chandrakasan
Massachusettes Institute of Technology
,
Sayfe Kiaei
Oregon State Univ., Corvallis

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 August 1997

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ISLPED97: 1997 International Symposium on Low Power Electronics and Design

August 18 - 20, 1997

California, Monterey, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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Kritikakou ACatthoor FKelefouras VGoutis C(2014)A scalable and near-optimal representation of access schemes for memory managementACM Transactions on Architecture and Code Optimization10.1145/257967711:1(1-25)Online publication date: 1-Feb-2014
https://dl.acm.org/doi/10.1145/2579677
Hayashizaki HSugawara YInaba MHiraki KMoshovos ATarditi DOlukotun K(2008)MCAMPProceedings of the 17th international conference on Parallel architectures and compilation techniques10.1145/1454115.1454132(102-111)Online publication date: 25-Oct-2008
https://dl.acm.org/doi/10.1145/1454115.1454132
Joo YChoi YPark JPark CChung SChung EChang N(2008)Energy and Performance Optimization of Demand Paging With OneNAND FlashIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.200608127:11(1969-1982)Online publication date: 1-Nov-2008
https://dl.acm.org/doi/10.1109/TCAD.2008.2006081
Issenin IBrockmeyer EMiranda MDutt N(2007)DRDUACM Transactions on Design Automation of Electronic Systems10.1145/1230800.123080712:2(15-es)Online publication date: 1-Apr-2007
https://dl.acm.org/doi/10.1145/1230800.1230807
Joo YChoi YPark CChung SChung EChang NBergamaschi RChoi K(2006)Demand paging for OneNAND™ Flash eXecute-in-placeProceedings of the 4th international conference on Hardware/software codesign and system synthesis10.1145/1176254.1176310(229-234)Online publication date: 22-Oct-2006
https://dl.acm.org/doi/10.1145/1176254.1176310
Hu QVandecappelle APalkovic MKjeldsberg PBrockmeyer ECatthoor FHirose F(2006)Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applicationsProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118442(606-611)Online publication date: 24-Jan-2006
https://dl.acm.org/doi/10.1145/1118299.1118442
Qubo Hu Vandecappelle APalkovic MKjeldsberg PBrockmeyer ECatthoor F(2006)Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applicationsAsia and South Pacific Conference on Design Automation, 2006.10.1109/ASPDAC.2006.1594752(606-611)Online publication date: 2006
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Macii EPedram MSomenzi F(2006)High-level power modeling, estimation, and optimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.73618117:11(1061-1079)Online publication date: 1-Nov-2006
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Kulkarni CCatthoor FDe Man H(2006)Hardware cache optimization for parallel multimedia applicationsEuro-Par’98 Parallel Processing10.1007/BFb0057949(923-932)Online publication date: 30-Jun-2006
https://doi.org/10.1007/BFb0057949
Baradaran NDiniz P(2005)Compiler-directed design space exploration for caching and prefetching data in high-level synthesisProceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.10.1109/FPT.2005.1568552(233-240)Online publication date: 2005
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Formalized methodology for data reuse exploration for low-power hierarchical memory mappings

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