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Network flow based multi-way partitioning with area and pin constraints

Authors:

Huiqun Liu,

D. F. WongAuthors Info & Claims

ISPD '97: Proceedings of the 1997 international symposium on Physical design

Pages 12 - 17

https://doi.org/10.1145/267665.267673

Published: 01 April 1997 Publication History

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Cited By

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Hur SLillis J(1999)Relaxation and clustering in a local search frameworkProceedings of the 36th annual ACM/IEEE Design Automation Conference10.1145/309847.309958(360-366)Online publication date: 1-Jun-1999
https://dl.acm.org/doi/10.1145/309847.309958
Sung-Woo Hur Lillis J(1999)Relaxation and clustering in a local search framework: application to linear placementProceedings 1999 Design Automation Conference (Cat. No. 99CH36361)10.1109/DAC.1999.781342(360-366)Online publication date: 1999
https://doi.org/10.1109/DAC.1999.781342
Cho JSarrafzadeh M(1999)Vlsi Circuit LayoutWiley Encyclopedia of Electrical and Electronics Engineering10.1002/047134608X.W1801Online publication date: 27-Dec-1999
https://doi.org/10.1002/047134608X.W1801
Show More Cited By

Index Terms

Network flow based multi-way partitioning with area and pin constraints
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Very large scale integration design
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory
      1. Paths and connectivity problems
  2. Mathematical software

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Network-flow-based multiway partitioning with area and pin constraints

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A timing-driven multi-way partitioning system for integrated circuits and multi-chip systems
SPECTRAL-BASED MULTI-WAY FPGA PARTITIONING

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Information

Published In

ISPD '97: Proceedings of the 1997 international symposium on Physical design

April 1997

230 pages

ISBN:0897919270

DOI:10.1145/267665

Chairmen:
Andrew B. Kahng
Univ. of California, Los Angeles, and Cadence Design Systems, San Jose, CA
,
Majid Sarrafzadeh
Northwestern Univ., Evanston, IL

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1997

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ISPD97: 1997 International Symposium on Physical Design

April 14 - 16, 1997

California, Napa Valley, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

View all

Hur SLillis J(1999)Relaxation and clustering in a local search frameworkProceedings of the 36th annual ACM/IEEE Design Automation Conference10.1145/309847.309958(360-366)Online publication date: 1-Jun-1999
https://dl.acm.org/doi/10.1145/309847.309958
Sung-Woo Hur Lillis J(1999)Relaxation and clustering in a local search framework: application to linear placementProceedings 1999 Design Automation Conference (Cat. No. 99CH36361)10.1109/DAC.1999.781342(360-366)Online publication date: 1999
https://doi.org/10.1109/DAC.1999.781342
Cho JSarrafzadeh M(1999)Vlsi Circuit LayoutWiley Encyclopedia of Electrical and Electronics Engineering10.1002/047134608X.W1801Online publication date: 27-Dec-1999
https://doi.org/10.1002/047134608X.W1801
Mak WWong D(1998)Performance-driven board-level routing for FPGA-based logic emulationProceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273)10.1109/ICCD.1998.727046(199-201)Online publication date: 1998
https://doi.org/10.1109/ICCD.1998.727046

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Network-flow-based multiway partitioning with area and pin constraints

A timing-driven multi-way partitioning system for integrated circuits and multi-chip systems

SPECTRAL-BASED MULTI-WAY FPGA PARTITIONING