research-article

Code generation from a domain-specific language for C-based HLS of hardware accelerators

Authors:

Richard Membarth,

Jürgen TeichAuthors Info & Claims

CODES '14: Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis

Article No.: 17, Pages 1 - 10

https://doi.org/10.1145/2656075.2656081

Published: 12 October 2014 Publication History

Abstract

As today's computer architectures are becoming more and more heterogeneous, a plethora of options including CPUs, GPUs, DSPs, reconfigurable logic (FPGAs), and other application-specific processors come into consideration for close-to-sensor processing. Especially, in the domain of image processing on mobile devices, among numerous design challenges, a very stringent energy budget is of utmost importance, making embedded GPUs and FPGAs ideal targets for implementation.

Recently, the HIPA^cc framework was proposed as a means for automatic code generation of image processing algorithms for embedded GPUs, based on a Domain-Specific Language (DSL). Despite of huge advancements in High-Level Synthesis (HLS) for FPGAs, designers are still required to have detailed knowledge about coding techniques and the targeted architecture to achieve efficient solutions. As a remedy, in this work, we propose code generation techniques for C-based HLS from a common high-level DSL description targeting FPGAs. Our approach includes FPGA-specific memory architectures for handling point and local operators, numerous high-level transformations, and automatic test bench generation. We evaluate our approach by comparing the resulting hardware accelerators to existing frameworks in terms of performance and resource requirements. Moreover, we assess the achieved energy efficiency in contrast to software implementations, generated by HIPA^cc from the same code base, executed on GPUs.

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Campos NEdirisinghe EChesnokov SLarkin D(2024)Fast Generation of Custom Floating-Point Spatial Filters on FPGAsIEEE Access10.1109/ACCESS.2024.348606612(167059-167071)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3486066
Kanetaka YTakagi HMaeda YFukushima N(2024)SlidingConv: Domain-Specific Description of Sliding Discrete Cosine Transform Convolution for HalideIEEE Access10.1109/ACCESS.2023.334566012(7563-7583)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2023.3345660
Liu QSetter JHuff DStrange MFeng KHorowitz MRaina PKjolstad F(2023)Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory AcceleratorsACM Transactions on Architecture and Code Optimization10.1145/357290820:2(1-26)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1145/3572908
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Published In

cover image ACM Conferences

CODES '14: Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis

October 2014

331 pages

ISBN:9781450330510

DOI:10.1145/2656075

Program Chairs:
Radu Marculescu
Carnegie Mellon University
,
Gabriela Nicolescu
Polytechnique Montréal

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 12 October 2014

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ESWEEK'14: TENTH EMBEDDED SYSTEM WEEK

October 12 - 17, 2014

New Delhi, India

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Cited By

Campos NEdirisinghe EChesnokov SLarkin D(2024)Fast Generation of Custom Floating-Point Spatial Filters on FPGAsIEEE Access10.1109/ACCESS.2024.348606612(167059-167071)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3486066
Kanetaka YTakagi HMaeda YFukushima N(2024)SlidingConv: Domain-Specific Description of Sliding Discrete Cosine Transform Convolution for HalideIEEE Access10.1109/ACCESS.2023.334566012(7563-7583)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2023.3345660
Liu QSetter JHuff DStrange MFeng KHorowitz MRaina PKjolstad F(2023)Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory AcceleratorsACM Transactions on Architecture and Code Optimization10.1145/357290820:2(1-26)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1145/3572908
Koul KMelchert JSreedhar KTruong LNyengele GZhang KLiu QSetter JChen PMei YStrange MDaly RDonovick CCarsello AKong TFeng KHuff DNayak ASetaluri RThomas JBhagdikar NDurst DMyers ZTsiskaridze NRichardson SBahr RFatahalian KHanrahan PBarrett CHorowitz MTorng CKjolstad FRaina P(2023)AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and CompilersACM Transactions on Embedded Computing Systems10.1145/353493322:2(1-34)Online publication date: 24-Jan-2023
https://dl.acm.org/doi/10.1145/3534933
Sozzo EConficconi DZeni ASalaris MSciuto DSantambrogio M(2022)Pushing the Level of Abstraction of Digital System Design: A Survey on How to Program FPGAsACM Computing Surveys10.1145/353298955:5(1-48)Online publication date: 3-Dec-2022
https://dl.acm.org/doi/10.1145/3532989
Huff DDai SHanrahan P(2021)Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAs2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM51124.2021.00030(186-194)Online publication date: May-2021
https://doi.org/10.1109/FCCM51124.2021.00030
Luthra SKhalid MMoin Oninda M(2020)FPGA-Based Evaluation and Implementation of an Automotive RADAR Signal Processing System using High-Level Synthesis2020 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)10.1109/CCECE47787.2020.9255725(1-6)Online publication date: 30-Aug-2020
https://doi.org/10.1109/CCECE47787.2020.9255725
Kalms LGöhringer D(2020)Accelerated High-Level Synthesis Feature Detection for FPGAs Using HiFlipVXTowards Ubiquitous Low-power Image Processing Platforms10.1007/978-3-030-53532-2_7(115-135)Online publication date: 16-Dec-2020
https://doi.org/10.1007/978-3-030-53532-2_7
Shi RWong JSo H(2019)High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image ProcessingJournal of Imaging10.3390/jimaging50300345:3(34)Online publication date: 6-Mar-2019
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Hoozemans JJong RVlugt SStraten JElango UAl-Ars Z(2019)Frame-based Programming, Stream-Based Processing for Medical Image Processing ApplicationsJournal of Signal Processing Systems10.1007/s11265-018-1422-391:1(47-59)Online publication date: 1-Jan-2019
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