Designing optimized forward residue number systems IP blocks converters from a network interface
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Abstract
Contemporary digital circuits demand a fast time to market period, and consequently a rapid prototype design exploration. Fast design space exploration requires tools that given a set of input constrains, generate the HDL definitions that implement the given functionality. Furthermore, residue number system (RNS), a non-conventional arithmetic system, has been proposed as a viable alternative for hardware acceleration, due to it's carry free nature. In this context, we present the first web accessible EDA tool that can generate custom synthesizable forward residue number binary-to-RNS converters, for a specific input bit width and a moduli base. To the best of our knowledge, our novel tool is the first one to automate the design of forward residue number system converters and simultaneously provide custom test benches to verify their correctness. Our synthesized circuits on Xilinx Virtex 6 FPGA, operate up to 783 Mhz.
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Index Terms
- Designing optimized forward residue number systems IP blocks converters from a network interface
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Published In
October 2014
355 pages
ISBN:9781450328975
DOI:10.1145/2645791
- General Chairs:
- Katsikas Sokratis,
- Hatzopoulos Michael,
- Apostolopoulos Theodoros,
- Anagnostopoulos Dimosthenis,
- Program Chairs:
- Carayiannis Elias,
- Varvarigou Theodora,
- Nikolaidou Mara
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In-Cooperation
- Greek Com Soc: Greek Computer Society
- Univ. of Piraeus: University of Piraeus
- National and Kapodistrian University of Athens: National and Kapodistrian University of Athens
- Athens U of Econ & Business: Athens University of Economics and Business
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 02 October 2014
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