research-article

Design space exploration for streaming applications on multiprocessors with guaranteed service NoC

Authors:

Usman Mazhar Mirza,

Flavius Gruian,

Krzysztof KuchcinskiAuthors Info & Claims

NoCArc '13: Proceedings of the Sixth International Workshop on Network on Chip Architectures

Pages 35 - 40

https://doi.org/10.1145/2536522.2536527

Published: 08 December 2013 Publication History

Abstract

This paper addresses design space exploration for streaming applications (such as MPEG) running on multi-processor platforms with guaranteed service interconnects. In particular, we solve mapping, path selection and router configuration problems. Given the complexity of these problems, state of the art approaches in this area largely rely on greedy heuristics, which do not guarantee optimality. Our approach is based on a constraint programming formulation that combines a number of steps, sequential in classical approaches. Thus, our method has the potential of finding optimal solutions with respect to resource usage under processing and bandwidth constraints. The experimental evaluation shows that our approach is capable of exploring a range of solutions while giving the designer the opportunity to emphasize the importance of various design metrics.

References

[1]

Adapteva Inc., http://www.adapteva.com/. Epiphany Architecture Reference (G3), revision 3.12.12.18 edition.

[2]

S. Bell et al. Tile64 - Processor: A 64-Core SoC with Mesh Interconnect. In Solid-State Circuits Conference, 2008.

[3]

G. Bilsen, M. Engels, R. Lauwereins, and J. Peperstraete. Cyclo-static data flow. In International Conference on Acoustics, Speech, and Signal Processing, 1995.

[4]

S. C. Brunet, M. Mattavelli, and J. W. Janneck. Profiling of dataflow programs using post mortem causation traces. In IEEE Workshop on Signal Processing Systems, 2012.

Digital Library

[5]

J. Buck and E. Lee. Scheduling dynamic dataflow graphs with bounded memory using the token flow model. In IEEE International Conference on Acoustics, Speech, and Signal Processing, 1993.

Digital Library

[6]

M. Butts. Synchronization through communication in a massively parallel processor array. Micro, IEEE, 27(5): 32--40, 2007.

Digital Library

[7]

J. Eker and J. W. Janneck. CAL language report specification of the CAL actor language. Technical report, University of California, Berkeley, 2003.

[8]

K. Goossens, J. Dielissen, and A. Rădulescu. Æthereal network on chip: concepts, architectures, and implementations. Design Test of Computers, IEEE, 22(5): 414--421, 2005.

Digital Library

[9]

A. Hansson, K. Goossens, and A. Rădulescu. A unified approach to mapping and routing on a network-on-chip for both best-effort and guaranteed service traffic. VLSI Design, 2007.

[10]

A. Hansson, M. Subburaman, and K. Goossens. aelite: a flit-synchronous network on chip with composable and predictable services. In Proceedings of the Conference on Design, Automation and Test in Europe, 2009.

Digital Library

[11]

J. Hu and R. Marculescu. Energy-aware mapping for tile-based NoC architectures under performance constraints. In Asia and South Pacific Design Automation Conference, 2003.

Digital Library

[12]

J. A. Kahle, M. N. Day, H. P. Hofstee, C. R. Johns, T. R. Maeurer, and D. J. Shippy. Introduction to the Cell multiprocessor. j-IBM-JRD, 49(4/5): 589--604, 2005.

Digital Library

[13]

K. Kuchcinski. Constraints-driven scheduling and resource assignment. ACM Transactions on Design Automation of Electronic Systems, 8(3): 355--383, 2003.

Digital Library

[14]

K. Kuchcinski and R. Szymanek. JaCoP Library. User's Guide. http://www.jacop.eu, 2013.

[15]

E. Lee and D. Messerschmitt. Synchronous data flow. Proceedings of the IEEE, pages 1235--1245, 1987.

[16]

Z. Lu and A. Jantsch. Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip. In G. G. E. Gielen, editor, ICCAD, pages 18--25, 2007.

Digital Library

[17]

S. Murali and G. De Micheli. Bandwidth-constrained mapping of cores onto NoC architectures. In Proc. of the conference on Design, automation and test in Europe, 2004.

Digital Library

[18]

P. Paulin. Programming challenges and solutions for multi-processor SoCs: An industrial perspective. In Design Automation Conference, 2011.

Digital Library

[19]

P. Shaw. A constraint for bin packing. In M. Wallace, editor, Principles and Practice of Constraint Programming, pages 648--662. Springer Berlin, 2004.

[20]

R. Stefan, A. Molnos, A. Ambrose, and K. Goossens. A TDM NoC supporting QoS, multicast, and fast connection set-up. In Proceedings of the Design, Automation and Test in Europe Conference, 2012.

Digital Library

[21]

R. Steiger. Network flow constraint. Semester Project, Laboratoire d'Intelligence Artificielle École Politechniqué Fédérale de Lausanne, 2010.

[22]

S. Stuijk, T. Basten, M. Geilen, and H. Corporaal. Multiprocessor resource allocation for throughput-constrained synchronous dataflow graphs. In Design Automation Conference, 2007.

Digital Library

[23]

S. Stuijk, M. Geilen, and T. Basten. SDF³: SDF for free. In Sixth International Conference on Application of Concurrency to System Design, 2006.

Digital Library

[24]

http://orcc.sourceforge.net. Open RVC-CAL compiler.

[25]

J. Wang, Y. Li, S. Chai, and Q. Peng. Bandwidth-aware application mapping for NoC-based MPSoCs. Journal of Computational Information Systems, 7(1): 152--159, 2011.

[26]

W. Zhou, Y. Zhang, and Z. Mao. An application specific NoC mapping for optimized delay. In International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006.

Cited By

Liu SLu ZJantsch AIvanov AMarculescu DPande PFlich JPattabiraman K(2015)Highway in TDM NoCsProceedings of the 9th International Symposium on Networks-on-Chip10.1145/2786572.2786577(1-8)Online publication date: 28-Sep-2015
https://dl.acm.org/doi/10.1145/2786572.2786577
Savas SGebrewahid EUl-Abdin ZNordstrom TYang M(2014)An evaluation of code generation of dataflow languages on manycore architectures2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications10.1109/RTCSA.2014.6910501(1-9)Online publication date: Aug-2014
https://doi.org/10.1109/RTCSA.2014.6910501
Mirza UGruian FKuchcinski K(2014)Mapping streaming applications on multiprocessors with time-division-multiplexed network-on-chipComputers and Electrical Engineering10.1016/j.compeleceng.2014.08.01540:8(276-291)Online publication date: 1-Nov-2014
https://dl.acm.org/doi/10.1016/j.compeleceng.2014.08.015

Recommendations

P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA
Abstract
The network-on-chip (NoC) has emerged as an efficient and scalable communication fabric for chip multiprocessors (CMPs) and multiprocessor system on chips (MPSoCs). The NoC architecture, the routers micro-architecture and links influence the ...
Design Exploration of Optical Interconnection Networks for Chip Multiprocessors
HOTI '08: Proceedings of the 2008 16th IEEE Symposium on High Performance Interconnects

The Network-on-Chip (NoC) paradigm has emerged as a promising solution for providing connectivity among the increasing number of cores that get integrated into both systems-on chip(SoC) and chip multiprocessors (CMP). In future high performance CMPs, ...
Exploration of distributed shared memory architectures for NoC-based multiprocessors

Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications. To enable MP-SoC platforms, scalable communication-centric interconnect fabrics, such as networks-on-chip (NoCs), have been recently ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Other conferences

NoCArc '13: Proceedings of the Sixth International Workshop on Network on Chip Architectures

December 2013

72 pages

ISBN:9781450323703

DOI:10.1145/2536522

General Chairs:
Maurizio Palesi
Kore University, Italy
,
Terrence Mak
The Chinese University of Hong Kong
,
Program Chair:
Masoud Daneshtalab
University of Turku, Finland

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 08 December 2013

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Research-article

Conference

NoCArc '13

NoCArc '13: Network on Chip Architectures

December 8, 2013

California, Davis, USA

Acceptance Rates

Overall Acceptance Rate 46 of 122 submissions, 38%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
102
Total Downloads

Downloads (Last 12 months)1
Downloads (Last 6 weeks)0

Reflects downloads up to 29 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Liu SLu ZJantsch AIvanov AMarculescu DPande PFlich JPattabiraman K(2015)Highway in TDM NoCsProceedings of the 9th International Symposium on Networks-on-Chip10.1145/2786572.2786577(1-8)Online publication date: 28-Sep-2015
https://dl.acm.org/doi/10.1145/2786572.2786577
Savas SGebrewahid EUl-Abdin ZNordstrom TYang M(2014)An evaluation of code generation of dataflow languages on manycore architectures2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications10.1109/RTCSA.2014.6910501(1-9)Online publication date: Aug-2014
https://doi.org/10.1109/RTCSA.2014.6910501
Mirza UGruian FKuchcinski K(2014)Mapping streaming applications on multiprocessors with time-division-multiplexed network-on-chipComputers and Electrical Engineering10.1016/j.compeleceng.2014.08.01540:8(276-291)Online publication date: 1-Nov-2014
https://dl.acm.org/doi/10.1016/j.compeleceng.2014.08.015

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten