research-article

A Side-channel Analysis Resistant Reconfigurable Cryptographic Coprocessor Supporting Multiple Block Cipher Algorithms

Authors:

Jie LiAuthors Info & Claims

DAC '14: Proceedings of the 51st Annual Design Automation Conference

Pages 1 - 6

https://doi.org/10.1145/2593069.2593077

Published: 01 June 2014 Publication History

Get Access

Abstract

A side-channel analysis resistant reconfigurable cryptographic coprocessor is designed and fabricated in 0.18μm CMOS with 1.8V supply and 100MHz frequency, supporting multiple block cipher algorithms of AES, DES, RC6 and IDEA. Our countermeasure utilizes idle processing elements existed in reconfigurable array to do dummy operations to hide leakage information. This method has little impact on area and frequency, and it is flexible after silicon. It resists SPA and DPA without distinguishing the encryption region. And by correlation-based electromagnetic analysis, measurement to disclosure of DES enhances 36 times with partial countermeasures and AES discloses no subkey after more than one million electromagnetic traces with full countermeasures.

References

[1]

D. Hwang, et al., AES-based Security Coprocessor IC in 0.18-μm CMOS With Resistance to Differential Power Analysis Side-Channel Attacks, J. Solid State Circuits, vol. 41, (Apr. 2006), 781--792.

Crossref

Google Scholar

[2]

M. Doulcier-Verdier, et al., A side-channel and fault-attack resistant AES circuit working on duplicated complemented values, In Proceedings of ISSCC Dig. Tech. Papers, (Feb. 2011), 274--275.

Google Scholar

[3]

C. Tokunaga, D. Blaauw, Secure AES engine with a local switched-capacitor current equalizer, In Proceedings of ISSCC Dig. Tech. Papers, (Feb. 2009), 274--275.

Google Scholar

[4]

J. Lee, et al., A 3.40ms/GF(p521) and DF-ECC Processor with side-channel attack resistance, In Proceedings of ISSCC Dig. Tech. Papers, (Feb. 2013), 50--51.

Google Scholar

[5]

S. Seyyedi, et al., "Securing Embedded Processor against Power Analysis based side channel attacks using reconfigurable architecture", In Proceedings of IFIP 9th International Conference on Embedded and Ubiquitous Computing, (Oct. 2011), 255--260.

Digital Library

Google Scholar

[6]

Weiwei Yan, Kaidi You, Jun Han, Xiaoyang Zeng. Low-cost reconfigurable VLSI implementation of the SMS4 and AES algorithms. In Proceedings of IEEE 8th International Conference on ASIC, (Oct. 2009), 135--138.

Google Scholar

[7]

Neil Smyth, Máire McLoone, John V McCanny. Reconfigurable Processor for Public-Key Cryptography. In Proceedings of IEEE workshop on Signal Processing Systems Design and Implementation, (Nov. 2005), 7803--9333.

Google Scholar

[8]

Weiwei Shan, Xin Chen, and et al., Evaluation of Correlation Power Analysis Resistance and Its Application on Asymmetric Mask Protected Data Encryption Standard Hardware, IEEE Trans. Instrum. Meas., 62,10 (Oct. 2013), 2716--2724.

Crossref

Google Scholar

[9]

Stefan Mangard, Elisabetn Oswald and Thomas Popp, Power Analysis Attacks. Springer Science+Business Media, LLC, (2007).

Google Scholar

[10]

Weiwei Shan, Xiao Zhang, and et al., VLSI Design of a Reconfigurable S-box Based on Memory Sharing Method, IEICE Electronics Express, 11, 1 (Jan. 2011), 1--6.

Google Scholar

[11]

Weiwei Shan, Xin Chen, Yinchao Lu, Xiao Zhang and Jie Li, Combinatorics-based Reconfigurable Bit Permutation Network with a Compact Structure, Chinese Journal of Electronics (to be published).

Google Scholar

Cited By

View all

Liu LWei SZhu JDeng CLiu LWei SZhu JDeng C(2022)Hardware Security and ReliabilitySoftware Defined Chips10.1007/978-981-19-7636-0_2(73-134)Online publication date: 15-Nov-2022
https://doi.org/10.1007/978-981-19-7636-0_2
Sasongko AKumara IWicaksana ARousseau FMuller O(2021)Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple StreamsACM Transactions on Reconfigurable Technology and Systems10.1145/346094114:3(1-25)Online publication date: 12-Aug-2021
https://dl.acm.org/doi/10.1145/3460941
Huang HYu BLiu ZWeng RGao JRen M(2018)DPA countermeasures for reconfigurable crypto processor using non-deterministic executionIEICE Electronics Express10.1587/elex.15.2018098715:24(20180987-20180987)Online publication date: 2018
https://doi.org/10.1587/elex.15.20180987
Show More Cited By

A Side-channel Analysis Resistant Reconfigurable Cryptographic Coprocessor Supporting Multiple Block Cipher Algorithms
1. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs

Recommendations

A Secure Reconfigurable Crypto IC With Countermeasures Against SPA, DPA, and EMA
A secure reconfigurable cryptographic co-processor supporting multiple algorithms of advanced encryption standard (AES), data encryption standard (DES), rivest cipher 6, and international data encryption algorithm is proposed using its own reconfigurable ...
On side-channel resistant block cipher usage
ISC'10: Proceedings of the 13th international conference on Information security

Based on re-keying techniques by Abdalla, Bellare, and Borst, we consider two black-box secure block cipher based symmetric encryption schemes, which we prove secure in the physically observable cryptography model. They are proven side-channel secure ...
Amplifying side-channel attacks with techniques from block cipher cryptanalysis
CARDIS'06: Proceedings of the 7th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications

We introduce the notion of amplified side-channel attacks, i.e. the application of block cipher cryptanalysis techniques to amplify effects exploitable by side-channel attacks. Such an approach is advantageous since it fully exploits the special ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

DAC '14: Proceedings of the 51st Annual Design Automation Conference

June 2014

1249 pages

ISBN:9781450327305

DOI:10.1145/2593069

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

In-Cooperation

EDAC: Electronic Design Automation Consortium
SIGBED: ACM Special Interest Group on Embedded Systems
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 2014

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed limited

Conference

DAC '14

DAC '14: The 51st Annual Design Automation Conference 2014

June 1 - 5, 2014

CA, San Francisco, USA

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

5
Total Citations
View Citations
206
Total Downloads

Downloads (Last 12 months)4
Downloads (Last 6 weeks)0

Reflects downloads up to 24 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Liu LWei SZhu JDeng CLiu LWei SZhu JDeng C(2022)Hardware Security and ReliabilitySoftware Defined Chips10.1007/978-981-19-7636-0_2(73-134)Online publication date: 15-Nov-2022
https://doi.org/10.1007/978-981-19-7636-0_2
Sasongko AKumara IWicaksana ARousseau FMuller O(2021)Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple StreamsACM Transactions on Reconfigurable Technology and Systems10.1145/346094114:3(1-25)Online publication date: 12-Aug-2021
https://dl.acm.org/doi/10.1145/3460941
Huang HYu BLiu ZWeng RGao JRen M(2018)DPA countermeasures for reconfigurable crypto processor using non-deterministic executionIEICE Electronics Express10.1587/elex.15.2018098715:24(20180987-20180987)Online publication date: 2018
https://doi.org/10.1587/elex.15.20180987
Wang BLiu LDeng CZhu MYin SWei S(2016)Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array ArchitectureIEEE Transactions on Information Forensics and Security10.1109/TIFS.2016.251813011:6(1151-1164)Online publication date: Jun-2016
https://doi.org/10.1109/TIFS.2016.2518130
Weiwei Shan Xingyuan Fu Zhipeng Xu (2015)A Secure Reconfigurable Crypto IC With Countermeasures Against SPA, DPA, and EMAIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.241962134:7(1201-1205)Online publication date: Jul-2015
https://doi.org/10.1109/TCAD.2015.2419621

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Recommendations

A Secure Reconfigurable Crypto IC With Countermeasures Against SPA, DPA, and EMA

On side-channel resistant block cipher usage

Amplifying side-channel attacks with techniques from block cipher cryptanalysis