poster

A comparison of core power gating strategies implemented in modern hardware

Authors:

Dean TullsenAuthors Info & Claims

SIGMETRICS '14: The 2014 ACM international conference on Measurement and modeling of computer systems

Pages 559 - 560

https://doi.org/10.1145/2591971.2592017

Published: 16 June 2014 Publication History

Get Access

Abstract

Idle power is a significant contributor to overall energy consumption in modern multi-core processors. Cores can enter a full-sleep state, also known as C6, to reduce idle power; however, entering C6 incurs performance and power overheads. Since power gating can result in negative savings, hardware vendors implement various algorithms to manage C6 entry. In this paper, we examine state-of-the-art C6 entry algorithms and present a comparative analysis in the context of consumer and CPU-GPU benchmarks.

References

[1]

http://www.hsafoundation.com.

Google Scholar

[2]

Pcmark 7 pc performance testing white paper, 2011.

Google Scholar

[3]

Bkdg for amd family 15h model processors, 2012.

Google Scholar

[4]

G. Blake et al. Evolution of thread-level parallelism in desktop applications. ISCA 2010.

Digital Library

Google Scholar

[5]

S. Che et al. Rodinia: A benchmark suite for heterogeneous computing. IISWC 2009.

Digital Library

Google Scholar

[6]

D. Foley et al. Amd llano fusion apu. HotChips 2011.

Google Scholar

[7]

H. Jiang. Intel next generation microarchitecture code named sandybridge. Intel Developer Forum, 2010.

Google Scholar

Cited By

View all

Sau CFanni TRubattu CRaffo LPalumbo F(2021)The Multi-Dataflow Composer toolMicroprocessors & Microsystems10.1016/j.micpro.2020.10332680:COnline publication date: 1-Feb-2021
https://dl.acm.org/doi/10.1016/j.micpro.2020.103326
Xue YLi JNazarian SBogdan P(2017)Fundamental Challenges Toward Making the IoT a Reachable RealityACM Transactions on Design Automation of Electronic Systems10.1145/300193422:3(1-25)Online publication date: 21-Apr-2017
https://dl.acm.org/doi/10.1145/3001934
Palumbo FFanni TSau CMeloni P(2017)Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional ArchitecturesJournal of Signal Processing Systems10.1007/s11265-016-1106-987:1(81-106)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1007/s11265-016-1106-9
Show More Cited By

Index Terms

A comparison of core power gating strategies implemented in modern hardware
1. General and reference
  1. Cross-computing tools and techniques
    1. Design

Recommendations

A comparison of core power gating strategies implemented in modern hardware
Performance evaluation review

Idle power is a significant contributor to overall energy consumption in modern multi-core processors. Cores can enter a full-sleep state, also known as C6, to reduce idle power; however, entering C6 incurs performance and power overheads. Since power ...
Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating
DAC '09: Proceedings of the 46th Annual Design Automation Conference

Process variability from a range of sources is growing as technology scales below 65nm, resulting in increasingly nonuniform transistor delay and leakage power both within a die and across dies. As a result, the negative impact of process variations on ...
Hardware-based load balancing for massive multicore architectures implementing power gating

Many-core architectures provide a computation platform with high execution throughput, enabling them to efficiently execute workloads with a significant degree of thread-level parallelism. The burstlike nature of these workloads allows large power ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

SIGMETRICS '14: The 2014 ACM international conference on Measurement and modeling of computer systems

June 2014

614 pages

ISBN:9781450327893

DOI:10.1145/2591971

General Chairs:
Sujay Sanghavi
The University of Texas at Austin
,
Sanjay Shakkottai
The University of Texas at Austin
,
Program Chairs:
Marc Lelarge
INRIA, France
,
Bianca Schroeder
University of Toronto

ACM SIGMETRICS Performance Evaluation Review Volume 42, Issue 1
Performance evaluation review
June 2014
569 pages
ISSN:0163-5999
DOI:10.1145/2637364
Editors:
Derek Eager
University of Saskatchewan
,
Carey Williamson
University of Calgary
Issue’s Table of Contents

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 16 June 2014

Check for updates

Author Tags

Qualifiers

Poster

Conference

SIGMETRICS '14

Sponsor:

SIGMETRICS

SIGMETRICS '14: ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems

June 16 - 20, 2014

Texas, Austin, USA

Acceptance Rates

SIGMETRICS '14 Paper Acceptance Rate 40 of 237 submissions, 17%;

Overall Acceptance Rate 459 of 2,691 submissions, 17%

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

8
Total Citations
View Citations
322
Total Downloads

Downloads (Last 12 months)7
Downloads (Last 6 weeks)5

Reflects downloads up to 21 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Sau CFanni TRubattu CRaffo LPalumbo F(2021)The Multi-Dataflow Composer toolMicroprocessors & Microsystems10.1016/j.micpro.2020.10332680:COnline publication date: 1-Feb-2021
https://dl.acm.org/doi/10.1016/j.micpro.2020.103326
Xue YLi JNazarian SBogdan P(2017)Fundamental Challenges Toward Making the IoT a Reachable RealityACM Transactions on Design Automation of Electronic Systems10.1145/300193422:3(1-25)Online publication date: 21-Apr-2017
https://dl.acm.org/doi/10.1145/3001934
Palumbo FFanni TSau CMeloni P(2017)Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional ArchitecturesJournal of Signal Processing Systems10.1007/s11265-016-1106-987:1(81-106)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1007/s11265-016-1106-9
Palumbo FFanni TSau CMeloni PRaffo L(2016)Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable ArchitecturesJournal of Electrical and Computer Engineering10.1155/2016/42373502016(5)Online publication date: 1-Nov-2016
https://dl.acm.org/doi/10.1155/2016/4237350
Zhao HKandemir MIrwin MNapoli CSalapura VFranke HHou R(2015)TaPErProceedings of the 12th ACM International Conference on Computing Frontiers10.1145/2742854.2742868(1-8)Online publication date: 6-May-2015
https://dl.acm.org/doi/10.1145/2742854.2742868
Malm NRuttik KTirkkonen O(2020)Latency-Aware Power Management in Software-Defined RadiosJournal of Electrical and Computer Engineering10.1155/2020/18548262020Online publication date: 11-Feb-2020
https://dl.acm.org/doi/10.1155/2020/1854826
Asad AOzturk OFathy MJahed-Motlagh M(2017)Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchyMicroprocessors and Microsystems10.1016/j.micpro.2017.03.01151(76-98)Online publication date: Jun-2017
https://doi.org/10.1016/j.micpro.2017.03.011
Duan LZhan DHohnerlein J(2015)Optimizing Cloud Data Center Energy Efficiency via Dynamic Prediction of CPU Idle IntervalsProceedings of the 2015 IEEE 8th International Conference on Cloud Computing10.1109/CLOUD.2015.133(985-988)Online publication date: 27-Jun-2015
https://dl.acm.org/doi/10.1109/CLOUD.2015.133

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

A comparison of core power gating strategies implemented in modern hardware

Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating

Hardware-based load balancing for massive multicore architectures implementing power gating