Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage
Article No.: 15, Pages 1 - 26
Abstract
Instruction set extensions (ISEs) improve the performance and energy consumption of application-specific processors. ISEs can use architecturally visible storage (AVS), localized compiler-controlled memories, to provide higher I/O bandwidth than reading data from the processor pipeline. AVS creates coherence and consistence problems with the data cache. Although a hardware coherence protocol could solve the problem, this approach is costly for a single-processor system. As a low-cost alternative, we introduce Virtual Ways, which ensures coherence through a reduced form of inclusion between the data cache and AVS. Virtual Ways achieve higher performance and lower energy consumption than using a hardware coherence protocol.
References
[1]
K. Atasu, W. Luk, O. Mencer, C. C. Özturan, and G. Dündar. 2012. FISH: Fast instruction synthesis for custom processors. IEEE Transactions on Very Large Scale Integration (TVLSI) Systems 20, 1, 52--65.
[2]
R. Banakar, S. Steinke, B.-S. Lee, M. Balakrishnan, and P. Marwedel. 2002. Scratchpad memory: A design alternative for cache on-chip memory in embedded systems. In Proceedings of the International Symposium on Hardware/Software Codesign. 73--78.
[3]
L. A. Barroso, K. Gharachorloo, R. Mcnamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, and B. Verghese. 2000. Piranha: A scalable architecture based on single-chip multiprocessing. In Proceedings of the International Symposium on Computer Architecture. 282--293.
[4]
P. Biswas, N. D. Dutt, L. Pozzi, and P. Ienne. 2007. Introduction of architecturally visible storage in instruction set extensions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, 3, 435--446.
[5]
J. Cong, Y. Fan, G. Han, A. Jagannathan, G. Reinman, and Z. Zhang. 2005. Instruction set extension with shadow registers for configurable processors. In Proceedings of the International Sympsosium on Field Programmable Gate Arrays. 99--106.
[6]
R. E. Gonzalez. 2000. Xtensa: A configurable and extensible processor. IEEE Micro 20, 2, 60--70.
[7]
R. E. Gonzalez. 2006. A software-configurable processor architecture. IEEE Micro 26, 5, 42--51.
[8]
T. R. Halfhill. 2000. EEMBC releases first benchmarks. Microprocessor Report, May 1, 2000.
[9]
T. R. Halfhill. 2003. Tensilica's software makes hardware. Microprocessor Report, June 23, 2003.
[10]
R. Hameed, W. Qadeer, M. Wachs, O. Azizi, A. Solomatnikov, B. C. Lee, S. Richardson, C. Kozyrakis, and M. Horowitz. 2011. Understanding sources of inefficiency in general-purpose chips. Communication of the ACM 54, 85--93.
[11]
A. Jaleel, E. Borch, M. Bhandaru, S. C. Steely Jr., and J. S. Emer. 2010. Achieving non-inclusive cache performance with inclusive caches: Temporal locality aware (TLA) cache management policies. In Proceedings of the International Symposium on Microarchitecture. 151--162.
[12]
R. Jayaseelan, H. Liu, and T. Mitra. 2006. Exploiting forwarding to improve data bandwidth of instruction-set extensions. In Proceedings of the Design Automation Conference. 43--48.
[13]
K. Karuri, A. Chattopadhyay, M. Hohenauer, R. Leupers, G. Ascheid, and H. Meyr. 2007. Increasing data-bandwidth to instruction-set extensions through register clusters. In Proceedings of the International Conference on Computer-Aided Design. 166--171.
[14]
T. Kluter. 2010. Architectural support for coherent architecturally visible storage in instruction set extensions. Ph.D. Dissertation. EPFL.
[15]
T. Kluter, P. Brisk, P. Ienne, and E. Charbon. 2008. Speculative DMA for architecturally visible storage in instruction set extensions. In Proceedings of the International Conference on Hardware-Software Codesign and System Synthesis. 243--248.
[16]
T. Kluter, P. Brisk, P. Ienne, and E. Charbon. 2009. Way stealing: cache-assisted automatic instruction set extensions. In Proceedings of the Design Automation Conference. 31--36.
[17]
T. Kluter, S. Burri, P. Brisk, E. Charbon, and P. Ienne. 2010. Virtual ways: efficient coherence for architecturally visible storage in automatic instruction set extensions. In Proceedings of the International Conference on High-Performance Embedded Architectures and Compilers. 126--140.
[18]
D. Lampret. 2006. OpenRISC 1000 Architecture Manual. Available at http://www.opencores.org/.
[19]
S. Mcfarling. 1992. Cache replacement with dynamic exclusion. In Proceedings of the International Symposium on Computer Architecture. 191--200.
[20]
L. Pozzi, K. Atasu, and P. Ienne. 2006. Exact and approximate algorithms for the extension of embedded processor instruction sets. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, 7, 1209--1229.
[21]
L. Pozzi and P. Ienne. 2005. Exploiting pipelining to relax register-file port constraints of instruction-set extensions. In Proceedings of the International Conference on Compilers Architecture, and Synthesis for Embedded Systems. 2--10.
[22]
A. Prakash, C. T. Clarke, and T. Srikanthan. 2012. Custom instructions with local memory elements without expensive DMA transfers. In Proceedings of the International Conference on Field Programmable Logic and Applications. 647--650.
[23]
T. Shyamkumar, M. Naveen, J. H. Ahn, and N. P. Jouppi. 2008. CACTI 5.1. Technical Report HPL-2008-20, HP Labs. Available online: http://www.hpl.hp.com/techreports/2008/HPL-2008-20.html.
[24]
A. K. Verma, P. Brisk, and P. Ienne. 2010. Fast, nearly optimal ISE identification with I/O serialization through maximal clique enumeration. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, 3, 341--354.
[25]
S. J. E. Wilton, and N. P. Jouppi. 1994. Tradeoffs in two-level on-chip caching. In Proceedings of the International Symposium on Computer Architecture. 34--45.
Index Terms
- Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage
Recommendations
Introduction of Architecturally Visible Storage in Instruction Set Extensions
Instruction set extensions (ISEs) can be used effectively to accelerate the performance of embedded processors. The critical and difficult task of ISE selection is often performed manually by designers. A few automatic methods for ISE generation have ...
Virtual ways: efficient coherence for architecturally visible storage in automatic instruction set extensions
HiPEAC'10: Proceedings of the 5th international conference on High Performance Embedded Architectures and CompilersCustomizable processors augmented with application-specific Instruction Set Extensions (ISEs) have begun to gain traction in recent years. The most effective ISEs include Architecturally Visible Storage (AVS), compiler-controlled memories accessible ...
Exploiting forwarding to improve data bandwidth of instruction-set extensions
DAC '06: Proceedings of the 43rd annual Design Automation ConferenceApplication-specific instruction-set extensions (custom instructions) help embedded processors achieve higher performance. Most custom instructions offering significant performance benefit require multiple input operands. Unfortunately, RISC-style ...
Comments
Please enable JavaScript to view thecomments powered by Disqus.Information & Contributors
Information
Published In
Copyright © 2014 ACM.
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 15 July 2014
Accepted: 01 January 2014
Revised: 01 November 2013
Received: 01 January 2012
Published in TACO Volume 11, Issue 2
Check for updates
Author Tags
Qualifiers
- Research-article
- Research
- Refereed
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 352Total Downloads
- Downloads (Last 12 months)46
- Downloads (Last 6 weeks)5
Reflects downloads up to 17 Nov 2024
Other Metrics
Citations
View Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in