research-article

Power optimization for clock network with clock gate cloning and flip-flop merging

Authors:

Chih-Cheng Hsu,

Mark Po-Hung LinAuthors Info & Claims

ISPD '14: Proceedings of the 2014 on International symposium on physical design

Pages 77 - 84

https://doi.org/10.1145/2560519.2560520

Published: 30 March 2014 Publication History

Abstract

Applying clock gates (CGs) and multi-bit flip-flops (MBFFs) are two of the most effective techniques for low power clock network design. Some previous works had proposed to optimize clock network with either CGs or MBFFs, but none of them simultaneously considers both CGs and MBFFs during clock network optimization. Although CGs and MBFFs can be optimized separately, the resulting dynamic power may not be optimal. This paper presents the first problem formulation in the literature for gated clock network optimization with simultaneous CG cloning and FF merging. To effectively solve the problem, a novel optimization flow consisting of MBFF-aware CG cloning, CG-based FF merging, and MBFF and CG placement optimization is introduced. Experimental results show that the proposed flow results in better dynamic power and clock wirelength compared with other flows which optimize gated clock network with CGs and MBFFs separately.

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Cited By

Sitik CLiu WTaskin BSalman EHomayoun HTaskin BMohsenin TZhao W(2019)Low Voltage Clock Tree Synthesis with Local Gate ClustersProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3318004(99-104)Online publication date: 13-May-2019
https://dl.acm.org/doi/10.1145/3299874.3318004
Seitanidis IDimitrakopoulos GMattheakis PMasse-Navette LChinnery D(2019)Timing-Driven and Placement-Aware Multibit Register CompositionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285274038:8(1501-1514)Online publication date: Aug-2019
https://doi.org/10.1109/TCAD.2018.2852740
Lee TPan DYang J(2018)Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing ConstraintIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.269802537:1(245-256)Online publication date: Jan-2018
https://doi.org/10.1109/TCAD.2017.2698025
Show More Cited By

Index Terms

Power optimization for clock network with clock gate cloning and flip-flop merging
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

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Published In

cover image ACM Conferences

ISPD '14: Proceedings of the 2014 on International symposium on physical design

March 2014

180 pages

ISBN:9781450325929

DOI:10.1145/2560519

General Chair:
Cliff Sze
IBM Research
,
Program Chair:
Azadeh Davoodi
University of Wisconsin - Madison

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 March 2014

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National Science Council Taiwan

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ISPD'14

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SIGDA

ISPD'14: International Symposium on Physical Design

March 30 - April 2, 2014

California, Petaluma, USA

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ISPD '14 Paper Acceptance Rate 14 of 40 submissions, 35%;

Overall Acceptance Rate 62 of 172 submissions, 36%

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ISPD '25

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International Symposium on Physical Design

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Cited By

Sitik CLiu WTaskin BSalman EHomayoun HTaskin BMohsenin TZhao W(2019)Low Voltage Clock Tree Synthesis with Local Gate ClustersProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3318004(99-104)Online publication date: 13-May-2019
https://dl.acm.org/doi/10.1145/3299874.3318004
Seitanidis IDimitrakopoulos GMattheakis PMasse-Navette LChinnery D(2019)Timing-Driven and Placement-Aware Multibit Register CompositionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285274038:8(1501-1514)Online publication date: Aug-2019
https://doi.org/10.1109/TCAD.2018.2852740
Lee TPan DYang J(2018)Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing ConstraintIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.269802537:1(245-256)Online publication date: Jan-2018
https://doi.org/10.1109/TCAD.2017.2698025
Gluzer DWimer S(2017)Probability-Driven Multibit Flip-Flop Integration With Clock GatingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.261400425:3(1173-1177)Online publication date: Mar-2017
https://doi.org/10.1109/TVLSI.2016.2614004
Lee TYi JYang J(2016)Multi-bit flip-flop generation considering multi-corner multi-mode timing constraint2016 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2016.7527357(782-785)Online publication date: May-2016
https://doi.org/10.1109/ISCAS.2016.7527357
Arumugam SViswanaathan L(2016)A novel PDWC‐UCO algorithm‐based buffer placement in FPGA architectureInternational Journal of Circuit Theory and Applications10.1002/cta.227745:4(550-570)Online publication date: 24-Oct-2016
https://doi.org/10.1002/cta.2277
Roy SPan DMattheakis PColyer PMasse-Navette LRibet PJones ALi HCoskun AMargala M(2015)Skew Bounded Buffer Tree Resynthesis For Clock Power OptimizationProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742119(87-90)Online publication date: 20-May-2015
https://dl.acm.org/doi/10.1145/2742060.2742119
Roy SMattheakis PMasse-Navette LPan D(2014)Evolving challenges and techniques for nanometer SoC clock network synthesis2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)10.1109/ICSICT.2014.7021158(1-4)Online publication date: Oct-2014
https://doi.org/10.1109/ICSICT.2014.7021158

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