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Optimal clock period FPGA technology mapping for sequential circuits

Authors:

Peichen Pan,

C. L. LiuAuthors Info & Claims

DAC '96: Proceedings of the 33rd annual Design Automation Conference

Pages 720 - 725

https://doi.org/10.1145/240518.240655

Published: 01 June 1996 Publication History

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Cited By

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Khurshid B(2017)LUT based realization of fixed-point multipliers targeting state-of-art FPGAsDesign Automation for Embedded Systems10.1007/s10617-017-9184-x21:2(89-115)Online publication date: 1-Jun-2017
https://dl.acm.org/doi/10.1007/s10617-017-9184-x
Pan P(2016)Sequential Circuit Technology MappingEncyclopedia of Algorithms10.1007/978-1-4939-2864-4_364(1952-1956)Online publication date: 22-Apr-2016
https://doi.org/10.1007/978-1-4939-2864-4_364
Pan P(2014)Sequential Circuit Technology MappingEncyclopedia of Algorithms10.1007/978-3-642-27848-8_364-2(1-5)Online publication date: 30-Dec-2014
https://doi.org/10.1007/978-3-642-27848-8_364-2
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Index Terms

Optimal clock period FPGA technology mapping for sequential circuits
1. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Sequential circuits

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Published In

DAC '96: Proceedings of the 33rd annual Design Automation Conference

June 1996

839 pages

ISBN:0897917790

DOI:10.1145/240518

Chairmen:
Thomas P. Pennino
Bell Labs, Holmdel, NJ
,
Ellen J. Yoffa
IBM Corp., Yorktown Heights, NY

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1996

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DAC96: The 33rd Design Automation Conference

June 3 - 7, 1996

Nevada, Las Vegas, USA

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DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Khurshid B(2017)LUT based realization of fixed-point multipliers targeting state-of-art FPGAsDesign Automation for Embedded Systems10.1007/s10617-017-9184-x21:2(89-115)Online publication date: 1-Jun-2017
Pan P(2016)Sequential Circuit Technology MappingEncyclopedia of Algorithms10.1007/978-1-4939-2864-4_364(1952-1956)Online publication date: 22-Apr-2016
Pan P(2014)Sequential Circuit Technology MappingEncyclopedia of Algorithms10.1007/978-3-642-27848-8_364-2(1-5)Online publication date: 30-Dec-2014
Cong JHu JKoh C(2012)Transformation from ad hoc EDA to algorithmic EDAProceedings of the 2012 ACM international symposium on International Symposium on Physical Design10.1145/2160916.2160929(57-62)Online publication date: 25-Mar-2012
Pan P(2008)Sequential Circuit Technology MappingEncyclopedia of Algorithms10.1007/978-0-387-30162-4_364(820-824)Online publication date: 2008
Hauck SDeHon A(2007)Reconfigurable ComputingundefinedOnline publication date: 2-Nov-2007
Chen DCong J(2004)DAOmapProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382677(752-759)Online publication date: 7-Nov-2004
Seidl UEckl KJohannes F(2003)Performance-Directed Retiming for FPGAs Using Post-Placement Delay InformationProceedings of the conference on Design, Automation and Test in Europe - Volume 110.5555/789083.1022818Online publication date: 3-Mar-2003
Eckl KMadre JZepter PLegl C(1999)A practical approach to multiple-class retimingProceedings of the 36th annual ACM/IEEE Design Automation Conference10.1145/309847.309920(237-242)Online publication date: 1-Jun-1999
Martin HRosenstiel WDewilde PRammig FMusgrave G(1998)A comparing study of technology mapping for FPGAProceedings of the conference on Design, automation and test in Europe10.5555/368058.368484(939-940)Online publication date: 23-Feb-1998
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Optimal clock period FPGA technology mapping for sequential circuits

Clock Power Analysis of Low Power Clock Gated Arithmetic Logic Unit on Different FPGA

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