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Concurrent analysis techniques for data path timing optimization

Published: 01 June 1996 Publication History
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References

[1]
H. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley Publishing Company, 1990.
[2]
C. Ewering, "Automated High Level Synthesis of Partitioned Busses," Proc. IEEE Int. Conf. Computer-Aided Design, pp 304-7, 1990
[3]
A. Jerraya and B. Courtois "The SYCO Silicon Comlier and its Environment," in Design Systems for VLSI Circuits, Martinus Nijhoff: Dordrecht. pp 499-526
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R. Leupers, E Marwedel, "A BDD-based Frontend for Retargetable Compilers," Proc. of the European Design Automation Conference, pp 239-243, 1995.
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T. Ly, W. Elwood, and E. Girczyc, "A Generalized Interconnect Model for Data Path Synthesis," 27th Design Automation Conference Proc., pp. 168-73, 1990.
[6]
C. Monahan, F. Brewer, "Communication Driven Interconnect Synthesis," 6th International Workshop on HLS Proc., pp 65-73, 1992.
[7]
C. Monahan, F. Brewer, "Symbolic Modeling and Evaluation of Data Paths," 32nd Design Automation Conference Proc., pp 389-94, 1995.
[8]
B. Pangrle, "Splicer: A Heuristic Approach to Connectivity Binding," 25th Design Automation Conference Proc., pp. 536-41, 1988
[9]
J. Rabaey, "CATHEDRAL-II: Computer-aided synthesis of digital processing systems," presented at the IEEE Custom Integrated Circuits Conf., May 1987.
[10]
A. Timmer, et. al, "Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores," 32nd Design Automation Conference Proc., pp.593-398, 1995.
[11]
C. Tseng and D. Siewiorek, "Automated Synthesis of Data Path in Digital Systems," IEEE Trans. on Computer-Aided Design, Vol. 5, No. 3, pp 379-95, July 1986.

Cited By

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  • (1997)Hierarchical test generation and design for testability of ASPPs and ASIPsProceedings of the 34th annual Design Automation Conference10.1145/266021.266277(534-539)Online publication date: 13-Jun-1997
  • (1996)Behavioral synthesisProceedings of the 33rd annual Design Automation Conference10.1145/240518.240524(33-34)Online publication date: 1-Jun-1996

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    cover image ACM Conferences
    DAC '96: Proceedings of the 33rd annual Design Automation Conference
    June 1996
    839 pages
    ISBN:0897917790
    DOI:10.1145/240518
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 01 June 1996

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    • (1997)Hierarchical test generation and design for testability of ASPPs and ASIPsProceedings of the 34th annual Design Automation Conference10.1145/266021.266277(534-539)Online publication date: 13-Jun-1997
    • (1996)Behavioral synthesisProceedings of the 33rd annual Design Automation Conference10.1145/240518.240524(33-34)Online publication date: 1-Jun-1996

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