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Error correction based on verification techniques

Authors:

Shi-Yu Huang,

Kuang-Chien Chen,

Kwang-Ting ChengAuthors Info & Claims

DAC '96: Proceedings of the 33rd annual Design Automation Conference

Pages 258 - 261

https://doi.org/10.1145/240518.240566

Published: 01 June 1996 Publication History

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References

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Cited By

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Chen FSu JLiu QZhou QBai B(2024)High efficiency error verification based on MET-LDPC codesProceedings of the 2024 International Conference on Computer and Multimedia Technology10.1145/3675249.3675303(304-307)Online publication date: 24-May-2024
https://dl.acm.org/doi/10.1145/3675249.3675303
Lee NKravets VJiang JParameswaran S(2017)Sequential engineering change order under retiming and resynthesisProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199715(109-116)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.5555/3199700.3199715
Ren HPuri RReddy LKrishnaswamy SWashburn CEarl JKeinert JMacii E(2013)Intuitive ECO synthesis for high performance circuitsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485529(1002-1007)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485529
Show More Cited By

Index Terms

Error correction based on verification techniques
1. Hardware
  1. Hardware validation
    1. Functional verification
2. Software and its engineering
  1. Software creation and management
    1. Software development techniques
      1. Error handling and recovery

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Information & Contributors

Information

Published In

DAC '96: Proceedings of the 33rd annual Design Automation Conference

June 1996

839 pages

ISBN:0897917790

DOI:10.1145/240518

Chairmen:
Thomas P. Pennino
Bell Labs, Holmdel, NJ
,
Ellen J. Yoffa
IBM Corp., Yorktown Heights, NY

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1996

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Conference

DAC96

Sponsor:

EDAC
SIGDA
IEEE-CAS

DAC96: The 33rd Design Automation Conference

June 3 - 7, 1996

Nevada, Las Vegas, USA

Acceptance Rates

DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Cited By

View all

Chen FSu JLiu QZhou QBai B(2024)High efficiency error verification based on MET-LDPC codesProceedings of the 2024 International Conference on Computer and Multimedia Technology10.1145/3675249.3675303(304-307)Online publication date: 24-May-2024
https://dl.acm.org/doi/10.1145/3675249.3675303
Lee NKravets VJiang JParameswaran S(2017)Sequential engineering change order under retiming and resynthesisProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199715(109-116)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.5555/3199700.3199715
Ren HPuri RReddy LKrishnaswamy SWashburn CEarl JKeinert JMacii E(2013)Intuitive ECO synthesis for high performance circuitsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485529(1002-1007)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485529
Tang KHuang PChou CHuang CRosenstiel WMacii E(2012)Multi-patch generation for multi-error logic rectification by interpolation with cofactor reductionProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2493091(1567-1572)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2493091
Tang KWu CHuang PHuang CStok LDutt NHassoun S(2011)Interpolation-based incremental ECO synthesis for multi-error logic rectificationProceedings of the 48th Design Automation Conference10.1145/2024724.2024758(146-151)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.1145/2024724.2024758
Wu BYang CHuang CJiang JScheffer LPhillips JHu A(2010)A robust functional ECO engine by SAT proof minimization and interpolation techniquesProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133584(729-734)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133584
Sen A(2007)Error Diagnosis in Equivalence Checking of High Performance MicroprocessorsElectronic Notes in Theoretical Computer Science (ENTCS)10.1016/j.entcs.2006.12.026174:4(9-18)Online publication date: 1-May-2007
https://dl.acm.org/doi/10.1016/j.entcs.2006.12.026
Veneris ALiu J(2005)Incremental Design Debugging in a Logic Synthesis EnvironmentJournal of Electronic Testing: Theory and Applications10.1007/s10836-005-0335-921:5(485-494)Online publication date: 1-Oct-2005
https://dl.acm.org/doi/10.1007/s10836-005-0335-9
Ubar R(2003)Design Error Diagnosis with Re-Synthesis in Combinational CircuitsJournal of Electronic Testing: Theory and Applications10.1023/A:102194801340219:1(73-82)Online publication date: 1-Feb-2003
https://dl.acm.org/doi/10.1023/A%3A1021948013402
Hoffmann DKropf T(2003)Automatic Error Correction of Large Circuits Using Boolean Decomposition and AbstractionCorrect Hardware Design and Verification Methods10.1007/3-540-48153-2_13(157-172)Online publication date: 3-Jun-2003
https://doi.org/10.1007/3-540-48153-2_13
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