research-article

Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description

Authors:

Harry Wagstaff,

Miles Gould,

Björn Franke,

Nigel TophamAuthors Info & Claims

DAC '13: Proceedings of the 50th Annual Design Automation Conference

Article No.: 21, Pages 1 - 6

https://doi.org/10.1145/2463209.2488760

Published: 29 May 2013 Publication History

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Abstract

Modern processor design tools integrate in their workflows generators for instruction set simulators (Iss) from architecture descriptions. Whilst these generated simulators are useful for design evaluation and software development, they suffer from poor performance. We present an ultra-fast Jit-compiled Iss generated from an ArchC description. We also introduce a novel partial evaluation optimisation, which further improves Jit compilation time and code quality. This results in a simulation rate of 510Mips for an Arm target across 45 Eembc and Spec benchmarks. On average, our Iss is 1.7 times faster than Simit-Arm, one of the fastest Iss generated from an architecture description.

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Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description

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Published In

DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGBED: ACM Special Interest Group on Embedded Systems

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Published: 29 May 2013

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Abstract

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Recommendations

Instruction set compiled simulation: a technique for fast and flexible instruction set simulation

A retargetable framework for instruction-set architecture simulation

A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation

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