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A hardware spinal decoder

Published: 29 October 2012 Publication History

Abstract

Spinal codes are a recently proposed capacity-achieving rateless code. While hardware encoding of spinal codes is straightforward, the design of an efficient, high-speed hardware decoder poses significant challenges. We present the first such decoder. By relaxing data dependencies inherent in the classic M-algorithm decoder, we obtain area and throughput competitive with 3GPP turbo codes as well as greatly reduced latency and complexity. The enabling architectural feature is a novel alpha-beta incremental approximate selection algorithm. We also present a method for obtaining hints which anticipate successful or failed decoding, permitting early termination and/or feedback-driven adaptation of the decoding parameters.
We have validated our implementation in FPGA with on-air testing. Provisional hardware synthesis suggests that a near-capacity implementation of spinal codes can achieve a throughput of 12.5 Mbps in a 65 nm technology while using substantially less area than competitive 3GPP turbo code implementations.

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Cited By

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  • (2020)Design of segmented CRC-aided spinal codes for IoT applicationsIET Communications10.1049/iet-com.2019.0907Online publication date: 30-Jul-2020
  • (2019)Compressive Spinal CodesIEEE Transactions on Vehicular Technology10.1109/TVT.2019.294702868:12(11944-11954)Online publication date: Dec-2019
  • (2019)A novel spinal codes based on chaotic Kent mapping2019 IEEE/CIC International Conference on Communications Workshops in China (ICCC Workshops)10.1109/ICCChinaW.2019.8849929(82-86)Online publication date: Aug-2019
  • Show More Cited By

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cover image ACM Conferences
ANCS '12: Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems
October 2012
270 pages
ISBN:9781450316859
DOI:10.1145/2396556
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 29 October 2012

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Author Tags

  1. architecture
  2. decoder
  3. rateless
  4. spinal
  5. wireless

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ANCS '12

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Overall Acceptance Rate 88 of 314 submissions, 28%

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Cited By

View all
  • (2020)Design of segmented CRC-aided spinal codes for IoT applicationsIET Communications10.1049/iet-com.2019.0907Online publication date: 30-Jul-2020
  • (2019)Compressive Spinal CodesIEEE Transactions on Vehicular Technology10.1109/TVT.2019.294702868:12(11944-11954)Online publication date: Dec-2019
  • (2019)A novel spinal codes based on chaotic Kent mapping2019 IEEE/CIC International Conference on Communications Workshops in China (ICCC Workshops)10.1109/ICCChinaW.2019.8849929(82-86)Online publication date: Aug-2019
  • (2018)Continuous wireless link rates for internet of thingsProceedings of the 17th ACM/IEEE International Conference on Information Processing in Sensor Networks10.1109/IPSN.2018.00012(48-59)Online publication date: 11-Apr-2018
  • (2017)Soft Hint Enabled Adaptive Visible Light Communication over Screen-Camera LinksIEEE Transactions on Mobile Computing10.1109/TMC.2016.255175016:2(527-537)Online publication date: 1-Feb-2017
  • (2016)SoftLight: Adaptive visible light communication over screen-camera linksIEEE INFOCOM 2016 - The 35th Annual IEEE International Conference on Computer Communications10.1109/INFOCOM.2016.7524510(1-9)Online publication date: Apr-2016

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