research-article

Using static analysis for coverage extraction fromemulation/prototyping platforms

Authors:

Viraj Athavale,

Shobha VasudevanAuthors Info & Claims

CODES+ISSS '12: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Pages 207 - 214

https://doi.org/10.1145/2380445.2380481

Published: 07 October 2012 Publication History

Abstract

Full-system emulation and prototyping is now being used widely in the industry for System-on-Chip (SoC) verification. Emulation/ prototyping platforms run tests in a fraction of time compared to the traditional simulation based verification. However, unlike simulation, they do not provide visibility into the hardware design source code. As a result, they fail to provide any information about code coverage achieved, which is an important metric to measure the completeness of the verification process.

In this paper, we present a novel technique to extract code coverage from emulation/prototyping platforms. Through analysis of the source code for the hardware design, we relate the evaluation of branch conditions to other statements in the code. Evaluation of the branch conditions is recorded using additional logic during emulation, and mapped back to the code to obtain coverage information. We apply our technique to an industrial system, and show that it can efficiently provide code coverage statistics that are faithful to the coverage obtained from simulation. We also perform experiments on the publicly available OpenRISC processor and demonstrate similar results.

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Cited By

Vasudevan S(2017)Still a Fight to Get It Right: Verification in the Era of Machine Learning2017 IEEE International Conference on Rebooting Computing (ICRC)10.1109/ICRC.2017.8123645(1-8)Online publication date: Nov-2017
https://doi.org/10.1109/ICRC.2017.8123645
Hertz SSheridan DVasudevan S(2013)Mining Hardware Assertions With Guidance From Static AnalysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.224117632:6(952-965)Online publication date: 1-Jun-2013
https://dl.acm.org/doi/10.1109/TCAD.2013.2241176

Index Terms

Using static analysis for coverage extraction fromemulation/prototyping platforms
1. Hardware
  1. Hardware validation
    1. Functional verification

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Published In

cover image ACM Conferences

CODES+ISSS '12: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

October 2012

596 pages

ISBN:9781450314268

DOI:10.1145/2380445

General Chairs:
Ahmed Jerraya
CEA
,
Luca Carloni
Columbia University
,
Program Chairs:
Naehyuck Chang
Seoul National University, Korea
,
Franco Fummi
University of Verona, Italy

Copyright © 2012 ACM.

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Published: 07 October 2012

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ESWEEK'12

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ESWEEK'12: Eighth Embedded System Week

October 7 - 12, 2012

Tampere, Finland

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CODES+ISSS '12 Paper Acceptance Rate 48 of 163 submissions, 29%;

Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

Vasudevan S(2017)Still a Fight to Get It Right: Verification in the Era of Machine Learning2017 IEEE International Conference on Rebooting Computing (ICRC)10.1109/ICRC.2017.8123645(1-8)Online publication date: Nov-2017
https://doi.org/10.1109/ICRC.2017.8123645
Hertz SSheridan DVasudevan S(2013)Mining Hardware Assertions With Guidance From Static AnalysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.224117632:6(952-965)Online publication date: 1-Jun-2013
https://dl.acm.org/doi/10.1109/TCAD.2013.2241176

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