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AMOR: an efficient aggregating based model order reduction method for many-terminal interconnect circuits

Published: 03 June 2012 Publication History

Abstract

In this paper, we propose an efficient Aggregating based Model Order Reduction method (AMOR) for many-terminal interconnect circuits. The proposed AMOR method is based on the observation that those adjacent nodes of interconnect circuits with almost the same voltage can be aggregated together as a "super node". Motivated by such an idea, we propose an efficient spectral partition algorithm in AMOR method to partition the nodes into groups with almost the same voltages. The reduced-order models are then obtained by aggregating the adjacent nodes within the same groups together as "super nodes" in AMOR method. The efficiency of AMOR method is not limited by the numbers of the terminals of the networks. Moreover, noticing that the aggregating procedure can be regarded as mapping the original problem into a coarse-grid problem in multigrid method, we propose a computation-efficient smoothing procedure to further improve the simulation accuracy of the reduced-order models. With such a strategy, the simulation accuracy of the reduced-order models can always be guaranteed. Numerical results have demonstrated that, without the smoothing procedure, the reduced-order models obtained by AMOR can still achieve higher simulation efficiency in terms of accuracy and CPU time than the reduced-order models obtained by the existing elimination based methods. With the smoothing procedure, the simulation accuracy of the reduced-order models can further be improved with several iterations.

References

[1]
P. Feldmann and F. Liu, "Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, Nov. 2004, pp. 88--92.
[2]
B. C. Moore, "Principal component analysis in linear systems: Controllability, observability, and model reduction," IEEE Trans. Automatic Control, vol. 35, no. 1, pp. 17--32, Feb. 1981.
[3]
J. Phillips and L. Silveira, "Poor man's TBR: A simple model reduction scheme," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 1, pp. 43--55, Jan. 2005.
[4]
L. Silveira and J. Phillips, "Exploiting input information in a model reduction algorithm for massively coupled parasitic networks," in Proceedings of IEEE/ACM Design Automation Conference. San Diego, June 2004, pp. 385--388.
[5]
P. Feldmann, "Model order reduction techniques for linear systems with large numbers of terminals," in Proceedings of IEEE/ACM Design, Automation and Test in Europe, 2004.
[6]
P. Li and W. Shi, "Model order reduction of linear networks with massive ports via frequency-dependent port packing," in IEEE/ACM DAC, 2006, pp. 267--272.
[7]
P. Liu, S. Tan, H. Li, Z. Qi, J. Kong, B. McGaughy, and L. He, "An efficient method for terminal reduction of interconnect circuits considering delay variations," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, 2005.
[8]
Z. Ye, D. Vasilyev, Z. Zhu, and J. R. Phillips, "Sparse implicit projection (sip) for reduction of general many-terminal networks," in Proc. ICCAD' 2008.
[9]
K. J. Kerns and A. T. Yang, "Stable and efficient reduction of large, multiport networks by pole analysis via congruence transformations," IEEE Trans. CAD, vol. 16, no. 7, pp. 734--744, July 1997.
[10]
B. N. Sheehan, "TICER: Realizable reduction of extracted RC circuits," in Proc. ICCAD '1999, pp. 200--203.
[11]
B. W. Kernighan and S. Lin, "An efficient heuristic procedure for partitioning graphs," Bell Syst. Tech. J., vol. 49, pp. 291--307, Feb. 1970.
[12]
C. M. Fiduccia and R. M. Mattheyses, "A linear-time heuristic for improving network partitions," in Proc. DAC, 1982, pp. 175--181.
[13]
E. R. Barnes, "An algorithm for partitioning the nodes of a graph," SIAM J. Alg. Disc. Meth., vol. 3, no. 4, pp. 541--550, 1970.
[14]
L. Hagen and A. B. Kahng, "Fast spectral methods for ratio cut partitioning and clustering," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, no. 9, pp. 1074--1085, 1992.
[15]
G. Golub and C. V. Loan, Matrix Computations. Baltimore: Johns Hopkins University Press, 1983.
[16]
T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein, Introduction to Algrorithms. The MIT Press, 2002, ch. 22.

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      cover image ACM Conferences
      DAC '12: Proceedings of the 49th Annual Design Automation Conference
      June 2012
      1357 pages
      ISBN:9781450311991
      DOI:10.1145/2228360
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 03 June 2012

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      Author Tags

      1. interconnect
      2. many-terminal
      3. model order reduction

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      DAC '12: The 49th Annual Design Automation Conference 2012
      June 3 - 7, 2012
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      Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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