Article

Performance-driven circuit partitioning for prototyping by using multiple FPGA chips

Authors:

Chunghee Kim,

Hyunchul Shin,

Young-Uk YuAuthors Info & Claims

ASP-DAC '95: Proceedings of the 1995 Asia and South Pacific Design Automation Conference

Pages 19 - es

https://doi.org/10.1145/224818.224886

Published: 01 August 1995 Publication History

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Mao FZhang WFeng BHe BMa YCoskun AMargala MBehjat LHan J(2016)Modular Placement for Interposer based Multi-FPGA SystemsProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2903025(93-98)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2902961.2903025
Nunna KMehdipour FMurakami K(2014)3D FPGA versus multiple FPGA systemProceedings of the Twelfth Australasian Symposium on Parallel and Distributed Computing - Volume 15210.5555/2667672.2667677(37-43)Online publication date: 20-Jan-2014
https://dl.acm.org/doi/10.5555/2667672.2667677
Lin P(2012)Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flatteningProceedings of the 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)10.1109/ICCD.2012.6378634(153-158)Online publication date: 30-Sep-2012
https://dl.acm.org/doi/10.1109/ICCD.2012.6378634
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Performance-driven circuit partitioning for prototyping by using multiple FPGA chips

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Architecture driven circuit partitioning

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This paper presents a prototyping verification methodology of SoC, and implements the prototyping verification of LEON3 SoC. First, it builds the FPGA prototyping hardware platform, completes transplanting an ASIC into a FPGA platform, finishes ...

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Published In

ASP-DAC '95: Proceedings of the 1995 Asia and South Pacific Design Automation Conference

August 1995

ISBN:0897917669

DOI:10.1145/224818

Chairman:
Isao Shirakawa
Osaka Univ., Osaka, Japan

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 August 1995

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ASPDAC95

Sponsor:

IFIP WG 10.2
IFIP WG 10.5
ISPJ
IEICE
SIGDA
IEEE-CAS

ASPDAC95: Asia Pacific Design Automation Conference

August 29 - September 1, 1995

Makuhari, Massa, Chiba, Japan

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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ASPDAC '25

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sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

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Mao FZhang WFeng BHe BMa YCoskun AMargala MBehjat LHan J(2016)Modular Placement for Interposer based Multi-FPGA SystemsProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2903025(93-98)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2902961.2903025
Nunna KMehdipour FMurakami K(2014)3D FPGA versus multiple FPGA systemProceedings of the Twelfth Australasian Symposium on Parallel and Distributed Computing - Volume 15210.5555/2667672.2667677(37-43)Online publication date: 20-Jan-2014
https://dl.acm.org/doi/10.5555/2667672.2667677
Lin P(2012)Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flatteningProceedings of the 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)10.1109/ICCD.2012.6378634(153-158)Online publication date: 30-Sep-2012
https://dl.acm.org/doi/10.1109/ICCD.2012.6378634
Johannes FPennino TYoffa E(1996)Partitioning of VLSI circuits and systemsProceedings of the 33rd annual Design Automation Conference10.1145/240518.240535(83-87)Online publication date: 1-Jun-1996
https://dl.acm.org/doi/10.1145/240518.240535
Johannes F(1996)Partitioning of VLSI circuits and systems33rd Design Automation Conference Proceedings, 199610.1109/DAC.1996.545551(83-87)Online publication date: 1996
https://doi.org/10.1109/DAC.1996.545551

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Architecture driven circuit partitioning

FPGA prototyping of a RISC processor core for embedded applications

The FPGA Prototyping Implementation of LEON3 SoC

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Architecture driven circuit partitioning

FPGA prototyping of a RISC processor core for embedded applications

The FPGA Prototyping Implementation of LEON3 SoC

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