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Fast identification of robust dependent path delay faults

Authors:

U. Sparmann,

D. Luxenburger,

K.-T. Cheng,

S. M. ReddyAuthors Info & Claims

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Pages 119 - 125

https://doi.org/10.1145/217474.217517

Published: 01 January 1995 Publication History

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Cited By

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Sun YMillican SAgrawal V(2020)Special Session: Survey of Test Point Insertion for Logic Built-in Self-test2020 IEEE 38th VLSI Test Symposium (VTS)10.1109/VTS48691.2020.9107584(1-6)Online publication date: Apr-2020
https://doi.org/10.1109/VTS48691.2020.9107584
Pomeranz IFettweis GNebel W(2014)Substituting transition faults with path delay faults as a basic delay fault modelProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616885(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616885
Pomeranz I(2013)Computing two-pattern test cubes for transition path delay faultsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218872721:3(475-485)Online publication date: 1-Mar-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2188727
Show More Cited By

Index Terms

Fast identification of robust dependent path delay faults
1. Hardware
  1. Hardware test
    1. Test-pattern generation and fault simulation
  2. Integrated circuits
    1. Logic circuits

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Information

Published In

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

January 1995

760 pages

ISBN:0897917251

DOI:10.1145/217474

Chairman:
Bryan T. Preas
Xerox Parc, Palo Alto, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 January 1995

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DAC95: The 32nd Design Automation Conference

June 12 - 16, 1995

California, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Sun YMillican SAgrawal V(2020)Special Session: Survey of Test Point Insertion for Logic Built-in Self-test2020 IEEE 38th VLSI Test Symposium (VTS)10.1109/VTS48691.2020.9107584(1-6)Online publication date: Apr-2020
https://doi.org/10.1109/VTS48691.2020.9107584
Pomeranz IFettweis GNebel W(2014)Substituting transition faults with path delay faults as a basic delay fault modelProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616885(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616885
Pomeranz I(2013)Computing two-pattern test cubes for transition path delay faultsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218872721:3(475-485)Online publication date: 1-Mar-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2188727
Pomeranz I(2012)On the detection of path delay faults by functional broadside tests2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS)10.1109/ETS.2012.6233015(1-6)Online publication date: May-2012
https://doi.org/10.1109/ETS.2012.6233015
Reddy S(2009)Models for Delay FaultsModels in Hardware Testing10.1007/978-90-481-3282-9_3(71-103)Online publication date: 27-Oct-2009
https://doi.org/10.1007/978-90-481-3282-9_3
Lu SHsieh PLiou JHassoun S(2006)Exploring linear structures of critical path delay faults to reduce test effortsProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233523(100-106)Online publication date: 5-Nov-2006
https://dl.acm.org/doi/10.1145/1233501.1233523
Ying-Yen Chen Min-Pin Kuo Jing-Jia Liou (2005)Diagnosis framework for locating failed segments of path delay faultsIEEE International Conference on Test, 2005.10.1109/TEST.2005.1583997(387-394)Online publication date: 2005
https://doi.org/10.1109/TEST.2005.1583997
Huang IGupta S(2005)Selection of Paths for Delay TestingProceedings of the 14th Asian Test Symposium on Asian Test Symposium10.1109/ATS.2005.97(208-215)Online publication date: 18-Dec-2005
https://dl.acm.org/doi/10.1109/ATS.2005.97
Fukunaga MKajihara STakeoka SYosimura SYasuura H(2003)On effective criterion of path selection for delay testingProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119941(757-762)Online publication date: 21-Jan-2003
https://dl.acm.org/doi/10.1145/1119772.1119941
Krasniewski A(2003)Evaluation of the quality of testing path delay faults under restricted input assumption9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003.10.1109/OLT.2003.1214393(168-170)Online publication date: 2003
https://doi.org/10.1109/OLT.2003.1214393
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