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Buffer insertion and sizing under process variations for low power clock distribution

Authors:

Joe G. Xi,

Wayne W. M. DaiAuthors Info & Claims

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Pages 491 - 496

https://doi.org/10.1145/217474.217576

Published: 01 January 1995 Publication History

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Joe G. Xi and Wayne W.M. Dai. Buffer insertion and sizing under process variations for low power clock distribution. In Technical Report, UCSC-CRL-95-12, University of California, Santa Cruz., 1995.

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Cited By

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Kim JKim T(2017)Boundary optimization of buffered clock trees for low powerIntegration, the VLSI Journal10.1016/j.vlsi.2016.10.00456:C(86-95)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.10.004
Guthaus M(2016)Clock Design and SynthesisElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-13(261-282)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-13
Ahn SKang MPapaefthymiou MKim T(2016)Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency ScalingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.254302235:12(2068-2081)Online publication date: 1-Nov-2016
https://dl.acm.org/doi/10.1109/TCAD.2016.2543022
Show More Cited By

Index Terms

Buffer insertion and sizing under process variations for low power clock distribution
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
      1. Datapath optimization
    2. Logic synthesis
      1. Circuit optimization

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Published In

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

January 1995

760 pages

ISBN:0897917251

DOI:10.1145/217474

Chairman:
Bryan T. Preas
Xerox Parc, Palo Alto, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 January 1995

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DAC95: The 32nd Design Automation Conference

June 12 - 16, 1995

California, San Francisco, USA

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Overall Acceptance Rate 299 of 1,119 submissions, 27%

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Cited By

View all

Kim JKim T(2017)Boundary optimization of buffered clock trees for low powerIntegration, the VLSI Journal10.1016/j.vlsi.2016.10.00456:C(86-95)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.10.004
Guthaus M(2016)Clock Design and SynthesisElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-13(261-282)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-13
Ahn SKang MPapaefthymiou MKim T(2016)Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency ScalingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.254302235:12(2068-2081)Online publication date: 1-Nov-2016
https://dl.acm.org/doi/10.1109/TCAD.2016.2543022
Arumugam SViswanaathan L(2016)A novel PDWC‐UCO algorithm‐based buffer placement in FPGA architectureInternational Journal of Circuit Theory and Applications10.1002/cta.227745:4(550-570)Online publication date: 24-Oct-2016
https://doi.org/10.1002/cta.2277
Lin MChih-Cheng Hsu Yu-Chuan Chen (2015)Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.237698834:2(280-292)Online publication date: Feb-2015
https://doi.org/10.1109/TCAD.2014.2376988
Wulong Liu Chen GYu Wang Huazhong Yang (2015)Modeling and optimization of low power resonant clock meshThe 20th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2015.7059052(478-483)Online publication date: Jan-2015
https://doi.org/10.1109/ASPDAC.2015.7059052
Hsu CLin MChang Y(2015)Crosstalk-aware multi-bit flip-flop generation for power optimizationIntegration, the VLSI Journal10.1016/j.vlsi.2014.08.00248:C(146-157)Online publication date: 1-Jan-2015
https://dl.acm.org/doi/10.1016/j.vlsi.2014.08.002
Hsu CChen YLin MHenkel J(2013)In-placement clock-tree aware multi-bit flip-flop generation for power optimizationProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561946(592-598)Online publication date: 18-Nov-2013
https://dl.acm.org/doi/10.5555/2561828.2561946
Guthaus MWilke GReis R(2013)Revisiting automated physical synthesis of high-performance clock networksACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244210218:2(1-27)Online publication date: 11-Apr-2013
https://dl.acm.org/doi/10.1145/2442087.2442102
Ahn SKang MKim T(2013)Power-aware inductor analysis in resonant clock networks2013 International SoC Design Conference (ISOCC)10.1109/ISOCC.2013.6863954(005-008)Online publication date: Nov-2013
https://doi.org/10.1109/ISOCC.2013.6863954
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