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Design-flow and synthesis for ASICs: a case study

Authors:

Massimo Bombana,

Patrizia Cavalloro,

Salvatore Conigliaro,

Roger B. Hughes,

Gerry Musgrave,

Giuseppe ZazaAuthors Info & Claims

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Pages 292 - 297

https://doi.org/10.1145/217474.217544

Published: 01 January 1995 Publication History

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Cited By

View all

(2002)Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-SiliconProceedings of the 2002 Asia and South Pacific Design Automation Conference10.5555/832284.835423Online publication date: 7-Jan-2002
https://dl.acm.org/doi/10.5555/832284.835423
Dislis CMusgrave GHughes R(1998)Formal design techniques-theory and engineering realityProceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259)10.1109/ATS.1998.741645(394-398)Online publication date: 1998
https://doi.org/10.1109/ATS.1998.741645
Bombana MHughes RMusgrave G(1995)A mathematically sound approach to the correct design of hardwareProceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair10.1109/ASPDAC.1995.486401(771-776)Online publication date: 1995
https://doi.org/10.1109/ASPDAC.1995.486401

Index Terms

Design-flow and synthesis for ASICs: a case study
1. Hardware

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Published In

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

January 1995

760 pages

ISBN:0897917251

DOI:10.1145/217474

Chairman:
Bryan T. Preas
Xerox Parc, Palo Alto, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 January 1995

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June 12 - 16, 1995

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

(2002)Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-SiliconProceedings of the 2002 Asia and South Pacific Design Automation Conference10.5555/832284.835423Online publication date: 7-Jan-2002
https://dl.acm.org/doi/10.5555/832284.835423
Dislis CMusgrave GHughes R(1998)Formal design techniques-theory and engineering realityProceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259)10.1109/ATS.1998.741645(394-398)Online publication date: 1998
https://doi.org/10.1109/ATS.1998.741645
Bombana MHughes RMusgrave G(1995)A mathematically sound approach to the correct design of hardwareProceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair10.1109/ASPDAC.1995.486401(771-776)Online publication date: 1995
https://doi.org/10.1109/ASPDAC.1995.486401

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Recommendations

Logic synthesis for ASICs

High-level synthesis of gracefully degradable ASICs

Efficient AES implementations on ASICs and FPGAs