Efficient in-system RTL verification and debugging using FPGAs (abstract only)
Authors: 
Proshanta Saha, Chuck Haymes, Ralph Bellofatto, Bernard Brezzo, Mohit Kapur, Sameh AsaadAuthors Info & Claims
Page 269
Abstract
FPGAs have become indispensible in processor design, bring-up and debug. Traditionally FPGAs have been used in prototyping, allowing end-users to emulate functionality of a specific component of a processor. However, as the complexity of processors grows, another aspect of processor design, RTL verification, has become a prime target for acceleration using FPGAs. Software-only RTL simulation and verification tools are no longer sufficient for many verification tasks as they often incur long execution time penalties. Software simulation time for a basic Linux kernel bring-up on a BlueGene/Q [1] processor, with 16 user PowerPC A2 cores, for example, could easily exceed several years.
An important feature of RTL verification acceleration using FPGAs is its fast debugging capabilities. The ability to quickly and accurately pinpoint the location of an anomaly in an RTL source is highly desirable. This paper proposes efficient in-system debugging techniques on FPGAs for RTL verification. We show how a network of over 45 Virtex 5 LX330 FPGAs can be efficiently used to read out state information of the BlueGene/Q processor. We also demonstrate how the new in-system debugging technique is 250x faster than comparable methods.
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S. Asaad, R. Bellofatto, B. Brezzo, C. Haymes, M. Kapur, B. Parker, T. Roewer, P. Saha, T. Takken, J. Tierno, "A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation", submitted for publication to the International Symposium on Field Programmable Gate Arrays (FPGA'12).
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- Efficient in-system RTL verification and debugging using FPGAs (abstract only)
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February 2012
352 pages
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Association for Computing Machinery
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Published: 22 February 2012
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FPGA '12
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FPGA '12: ACM/SIGDA International Symposium on Field Programmable Gate Arrays
February 22 - 24, 2012
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