research-article

Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library

Authors:

Alessandro Cevrero,

Francesco Regazzoni,

Micheal Schwander,

Stephane Badel,

Yusuf LeblebiciAuthors Info & Claims

DAC '11: Proceedings of the 48th Design Automation Conference

Pages 1014 - 1019

https://doi.org/10.1145/2024724.2024947

Published: 05 June 2011 Publication History

Abstract

MOS Current Mode Logic (MCML) is one of the most promising logic style to counteract power analysis attacks. Unfortunately, the static power consumption of MCML standard cells is significantly higher compared to equivalent functions implemented using static CMOS logic. As a result, the use of such a logic style is very limited in portable devices. Paradoxically, these devices are the most sensitive to physical attacks, thus the ones which would benefit more from the adoption of MCML.

We propose to overcome this limitation by reducing drastically the static power consumption of MCML-based cryptographic circuits. To this end, we designed Power Gated MCML (PG-MCML), a standard cell library featuring a sleep transistor in every cell. The effects of the sleep transistor on performance as well as on area are negligible. Moreover, the proposed differential library is supported by conventional EDA tools.

We evaluated our standard cell library using Advanced Encryption Standard (AES) as benchmark and we compared the power consumption, the area, and the DPA-resistance figures with the ones of static CMOS and conventional MCML. Our results show that our PG-MCML library can achieve a power consumption comparable with the one of static CMOS, thus proving that PG-MCML cells can suit the strict power budget of battery operated devices.

References

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Cited By

Singha TPalathinkal RAhamed S(2023)Securing AES Designs Against Power Analysis Attacks: A SurveyIEEE Internet of Things Journal10.1109/JIOT.2023.326568310:16(14332-14356)Online publication date: 15-Aug-2023
https://doi.org/10.1109/JIOT.2023.3265683
Tena-Sánchez EPotestad-Ordóñez FJiménez-Fernández CAcosta AChaves R(2022)Gate-Level Hardware Countermeasure Comparison against Power Analysis AttacksApplied Sciences10.3390/app1205239012:5(2390)Online publication date: 25-Feb-2022
https://doi.org/10.3390/app12052390
Liu YHe JMa HQu TDai Z(2022)A Comprehensive Evaluation of Integrated Circuits Side-Channel Resilience Utilizing Three-Independent-Gate Silicon Nanowire Field Effect Transistors-Based Current Mode LogicIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.312836441:10(3228-3238)Online publication date: Oct-2022
https://doi.org/10.1109/TCAD.2021.3128364
Show More Cited By

Index Terms

Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library
1. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors

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Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '11: Proceedings of the 48th Design Automation Conference

June 2011

1055 pages

ISBN:9781450306362

DOI:10.1145/2024724

General Chair:
Leon Stok
IBM Corp., Hopewell Jct., NY
,
Program Chairs:
Nikil Dutt
Univ. of California, Irvine, CA
,
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE Council on Electronic Design Automation (CEDA)

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 June 2011

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DAC '11

Sponsor:

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DAC '11: The 48th Annual Design Automation Conference 2011

June 5 - 10, 2011

California, San Diego

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Singha TPalathinkal RAhamed S(2023)Securing AES Designs Against Power Analysis Attacks: A SurveyIEEE Internet of Things Journal10.1109/JIOT.2023.326568310:16(14332-14356)Online publication date: 15-Aug-2023
https://doi.org/10.1109/JIOT.2023.3265683
Tena-Sánchez EPotestad-Ordóñez FJiménez-Fernández CAcosta AChaves R(2022)Gate-Level Hardware Countermeasure Comparison against Power Analysis AttacksApplied Sciences10.3390/app1205239012:5(2390)Online publication date: 25-Feb-2022
https://doi.org/10.3390/app12052390
Liu YHe JMa HQu TDai Z(2022)A Comprehensive Evaluation of Integrated Circuits Side-Channel Resilience Utilizing Three-Independent-Gate Silicon Nanowire Field Effect Transistors-Based Current Mode LogicIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.312836441:10(3228-3238)Online publication date: Oct-2022
https://doi.org/10.1109/TCAD.2021.3128364
Tehranipoor MPundir NVashistha NFarahmandi FTehranipoor MPundir NVashistha NFarahmandi F(2022)Hardware Security Primitives Based on Emerging TechnologiesHardware Security Primitives10.1007/978-3-031-19185-5_9(145-169)Online publication date: 12-Oct-2022
https://doi.org/10.1007/978-3-031-19185-5_9
Das SChen AMarinella M(2021)Beyond CMOS2021 IEEE International Roadmap for Devices and Systems Outbriefs10.1109/IRDS54852.2021.00011(01-129)Online publication date: Nov-2021
https://doi.org/10.1109/IRDS54852.2021.00011
Naveenkumar RSivamangai NNapolean AJanani V(2021)A Survey on Recent Detection Methods of the Hardware Trojans2021 3rd International Conference on Signal Processing and Communication (ICPSC)10.1109/ICSPC51351.2021.9451682(139-143)Online publication date: 13-May-2021
https://doi.org/10.1109/ICSPC51351.2021.9451682
Regazzoni FPolian IMohsenin TZhao WChen YMutlu O(2020)Side Channel Attacks vs Approximate ComputingProceedings of the 2020 on Great Lakes Symposium on VLSI10.1145/3386263.3407592(321-326)Online publication date: 7-Sep-2020
https://dl.acm.org/doi/10.1145/3386263.3407592
Zarrinchian GSaheb Zamani M(2019)Combinational Counters: A Low Overhead Approach to Address DPA AttacksJournal of Circuits, Systems and Computers10.1142/S0218126620500978Online publication date: 17-Jul-2019
https://doi.org/10.1142/S0218126620500978
Gupta KPandey NGupta MGupta KPandey NGupta M(2019)IntroductionModel and Design of Improved Current Mode Logic Gates10.1007/978-981-15-0982-7_1(1-11)Online publication date: 23-Nov-2019
https://doi.org/10.1007/978-981-15-0982-7_1
Zoni DBarenghi APelosi GFornaciari W(2018)A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU MicroarchitectureACM Transactions on Design Automation of Electronic Systems10.1145/321271923:5(1-30)Online publication date: 20-Aug-2018
https://dl.acm.org/doi/10.1145/3212719
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