research-article

Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect

Authors:

Kanak AgarwalAuthors Info & Claims

DAC '11: Proceedings of the 48th Design Automation Conference

Pages 534 - 539

https://doi.org/10.1145/2024724.2024848

Published: 05 June 2011 Publication History

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Abstract

Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation techniques to reduce the detrimental effects of delay variations, particularly those that occur within-die, new methods of measuring delay variations within actual products are needed. The data provided by such techniques can also be used for validating models, i.e., can assist with model-to-hardware correlation. In this paper, we propose a flush delay technique for measuring both regional delay variations and SOI history effect and validate the method using a test structure fabricated in a 65 nm SOI process.

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Cited By

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HU YYE JSHI ZLI X(2017)LAPS: Layout-Aware Path Selection for Post-Silicon Timing CharacterizationIEICE Transactions on Information and Systems10.1587/transinf.2016EDP7184E100.D:2(323-331)Online publication date: 2017
https://doi.org/10.1587/transinf.2016EDP7184
Del Barrio ACong JHermida R(2016)A Distributed Clustered Architecture to Tackle Delay Variations in Datapath SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.247436235:3(419-432)Online publication date: 1-Mar-2016
https://dl.acm.org/doi/10.1109/TCAD.2015.2474362
Saqib FIsmari DLamech CPlusquellic J(2015)Within-Die Delay Variation Measurement and Power Transient Analysis Using REBELIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.231830723:4(776-780)Online publication date: Apr-2015
https://doi.org/10.1109/TVLSI.2014.2318307
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Index Terms

Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect
1. Hardware
  1. Hardware validation

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Information

Published In

DAC '11: Proceedings of the 48th Design Automation Conference

June 2011

1055 pages

ISBN:9781450306362

DOI:10.1145/2024724

General Chair:
Leon Stok
IBM Corp., Hopewell Jct., NY
,
Program Chairs:
Nikil Dutt
Univ. of California, Irvine, CA
,
Soha Hassoun
Tufts Univ., Medford, MA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 June 2011

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DAC '11: The 48th Annual Design Automation Conference 2011

June 5 - 10, 2011

California, San Diego

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

HU YYE JSHI ZLI X(2017)LAPS: Layout-Aware Path Selection for Post-Silicon Timing CharacterizationIEICE Transactions on Information and Systems10.1587/transinf.2016EDP7184E100.D:2(323-331)Online publication date: 2017
https://doi.org/10.1587/transinf.2016EDP7184
Del Barrio ACong JHermida R(2016)A Distributed Clustered Architecture to Tackle Delay Variations in Datapath SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.247436235:3(419-432)Online publication date: 1-Mar-2016
https://dl.acm.org/doi/10.1109/TCAD.2015.2474362
Saqib FIsmari DLamech CPlusquellic J(2015)Within-Die Delay Variation Measurement and Power Transient Analysis Using REBELIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.231830723:4(776-780)Online publication date: Apr-2015
https://doi.org/10.1109/TVLSI.2014.2318307
Khan AOhnari YDutta ASingh SMiura-Mattausch MMattausch H(2013)Die-to-die and within-die fabrication variation of 65nm CMOS technology PMOS transistors2013 IEEE International Conference on Electronics, Computing and Communication Technologies10.1109/CONECCT.2013.6469286(1-6)Online publication date: Jan-2013
https://doi.org/10.1109/CONECCT.2013.6469286
Wang TQuan GRen SQiu M(2012)Topology Virtualization for Throughput Maximization on Many-Core PlatformsProceedings of the 2012 IEEE 18th International Conference on Parallel and Distributed Systems10.1109/ICPADS.2012.63(408-415)Online publication date: 17-Dec-2012
https://dl.acm.org/doi/10.1109/ICPADS.2012.63
Lamech CAarestad JPlusquellic JRad RAgarwal KPhillips JHu AGraeb H(2011)REBEL and TDCProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132365(170-177)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132365
Lamech CAarestad JPlusquellic JRad RAgarwal K(2011)REBEL and TDCProceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design10.1109/ICCAD.2011.6105322(170-177)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.1109/ICCAD.2011.6105322

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A Statistical Design-Oriented Delay Variation Model Accounting for Within-Die Variations

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Mapping Statistical Process Variations Toward Circuit Performance Variability: An Analytical Modeling Approach