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Analysis of the conditional skip instructions of the HP precision architecture

Published: 30 November 1994 Publication History

Abstract

The HP-PA instruction set allows any arithmetic instruction to conditionally skip the following instruction based on the result of the arithmetic calculation. We have isolated this architectural feature and measured its performance benefit on a set of SPEC benchmark programs. Results indicate that adding the ability to skip to arithmetic instructions yields only a marginal performance benefit (less than 0.3%) for floating point intensive programs. For integer programs, however, the average benefit is between 0.6 and 2.8%. Most of this benefit comes from using arithmetic nullification with the COMICLR and COMCLR instructions. Our results assume a scalar processor, and therefore provide a lower bound on the performance benefit for more aggressive implementations.

References

[1]
T. Asprey, G. S. AverilI, E. DeLano, R. Mason, B. Wether, and J. Yetter. Performance features of the PA7100 microprocessor. IEEE Micro, pages 22- 35, June 1993.
[2]
P. P. Chang, S. A. Mahlke, W. Y. Chen, N. J. Wafter, et al. IMPACT: an architectural framework for multiple-instruction-issue processors. In Proceedings of the 18th Annual International Symposium on Computer Architecture, pages 266-275, 1991.
[3]
J. R. Larus. Efficient program tracing. Computer, 26(5):52-61, May 1993.
[4]
R. Lee, M. Mahon, and D. Morris. Pathlength reduction features in the PA-RISC architecture. In COMPCON, pages 129-135, 1992.
[5]
K. W. Pettis and W. B. Buzbee. Hewlett- Packard Precision Architecture compiler performance. Hewlett-Packard Journal, pages 29-37, Mar. 1987.
[6]
D. P. Siewiorek, C. G. Bell, and A. Newell. Computer Structures: Principles and Examples. McGraw-Hill, 1982.
[7]
J. P. Vogel. Performance analysis of conditionally nullifying arithmetic instructions in the Hewlett- Packard Precision Architecture. Master's thesis, Northwestern University, 1993.

Cited By

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  • (2010)Trading Conditional Execution for More Registers on ARM ProcessorsProceedings of the 2010 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing10.1109/EUC.2010.18(53-59)Online publication date: 11-Dec-2010
  • (1999)Control Flow: Branching and Control HazardsThe Microarchitecture of Pipelined and Superscalar Computers10.1007/978-1-4757-2989-4_4(83-150)Online publication date: 1999
  • (1997)PA-8000: a case study of static and dynamic branch predictionProceedings International Conference on Computer Design VLSI in Computers and Processors10.1109/ICCD.1997.628855(97-105)Online publication date: 1997

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cover image ACM Conferences
MICRO 27: Proceedings of the 27th annual international symposium on Microarchitecture
November 1994
233 pages
ISBN:0897917073
DOI:10.1145/192724
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 30 November 1994

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MICRO94
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MICRO94: 27th Annual International Symposium on Microarchitecture
November 30 - December 2, 1994
California, San Jose, USA

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Cited By

View all
  • (2010)Trading Conditional Execution for More Registers on ARM ProcessorsProceedings of the 2010 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing10.1109/EUC.2010.18(53-59)Online publication date: 11-Dec-2010
  • (1999)Control Flow: Branching and Control HazardsThe Microarchitecture of Pipelined and Superscalar Computers10.1007/978-1-4757-2989-4_4(83-150)Online publication date: 1999
  • (1997)PA-8000: a case study of static and dynamic branch predictionProceedings International Conference on Computer Design VLSI in Computers and Processors10.1109/ICCD.1997.628855(97-105)Online publication date: 1997

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