Data flow partitioning for clock period and latency minimization

It is known that the clock skew can be exploited as a manageableresource to improve the circuit performance. However, due to thelimitation of race condition, the optimal clock skew schedulingdoes not achieve the lower bound of the clock period. In ...

In high-performance nanometer synchronous chip design, a buffered clock tree with high tolerance of process variations is essential. The nominal clock skew always plays a crucial role in determining circuit performance and thus should be a first-order ...

Although intentional clock skew can be utilized to reduce the clock period, its application in gated clock designs has not been well studied. A gated clock design includes both data paths and clock control paths, but conventional clock skew scheduling ...