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The attributed-behavior abstraction and synthesis tools

Authors:

Lawrence F. Arnstein,

Don ThomasAuthors Info & Claims

DAC '94: Proceedings of the 31st annual Design Automation Conference

Pages 557 - 561

https://doi.org/10.1145/196244.196552

Published: 06 June 1994 Publication History

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References

[1]

Abramson, J.M., Birmingham, W.E, Binding and Scheduling under External Timing Constraints: The ARIEL Synthesis System, Technical Report Number CSE-TR-83-91, Computer Science and Engineering Division, Electrical Engineering and Computer Science Department, University of Michigan.]]

[2]

Arnstein, L.F., Thomas, D.E., "A General Consistency Technique for Increasing the Controllability of High Level Synthesis Tools", Proceedings of the IEEE/ACM International Conference on Computer Aided Design, California, November, 1993, pp. 741-744.]]

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[3]

Arnstein, L.E, A High-Level Synthesis Based VLSI Design Methodology, Ph.D. Thesis, Department of Electrical and Computer Engineer, Carnegie Mellon University, Pennsylvania, Dec. 1993.]]

Digital Library

[4]

Arnstein, L.F., Thomas, D.E., "Applications of Attributed-Behavior Synthesis", The Proceedings of the 7th IEEE/ACM International Symposium on High-Level Synthesis, Ontario, April 1994.]]

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Bergamaschi, R.A., Camposano, R., Payer, M., "Scheduling Under Resource Constraints and Module Assignment", INTEGRATION, vol. 12, December 1991.]]

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Camposano, R., Kunzmann, A., "Considering Timing Constraints in Synthesis From a Behavioral Description", Proceedings of the International COnference on Computer Design, November 1986.]]

[7]

Cloutier, R., "Force Directed Scheduling Allocation and Mapping", Proceedings of the 27th ACM/IEEE Design Automation Conference, pp. 71-76, 1990.]]

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Devadas, S., Newton, A.R., "Algorithms for Hardware Allocation in Data-Path Synthesis", IEEE Transactions on Computer Aided Design, Vol 8., No. 7, July 1989, pp. 768-779.]]

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[9]

Ku, D.C., De Michelli, G., Relative Scheduling under Timing Constraints: "Algorithms for High Level Synthesis of Digital Circuits", IEEE Transactions on Computer Aided Design, Vol 11, No 6, June 1992, pp 696.]]

[10]

Lagnese, E., Architectural Partitioning for System Level Design of Integrated Circuits, Ph.D. Thesis, Carnegie Mellon University, ECE Department, 1989.]]

[11]

Paulin, E, High Level Synthesis of Digital Circuits Using Global Scheduling and Binding Heuristics, Ph.D. Thesis, Department of Electronics, Faculty of Engineering, Carleton University, January 1988.]]

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Powell, E, Sequence Similarity Algorithms and a Linear Systolic Implementation, Technical Report TR 89-44, Computer Science Department, Institute of Technology University of Minnesota, Minneapolis, Minnesota, 1989.]]

[13]

Rao, D.S., Kurdahi, EJ., "Hierarchical Design Space Exploration for a Class of Digital Systems", IEEE Transactions of Very Large Scale Integration Systems, Vol 1, No 3, September 1993, pp. 282- 295.]]

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Schmit, H., Arnstein, L.E, Thomas, D., Lagnese, B., "Behavioral Synthesis for FPGA Based Computing", IEEE Workshop on FPGA's for Custom Computing, April, 1994.]]

[15]

Thomas, D., The System Architect's Workbench User's Guide, Technical Report CMUCAD-91-42, Department of Electrical and Computer Engineering, Carnegie Mellon University, May 1991.]]

Cited By

Economakos G(2006)Behavioral Synthesis with SystemC and PSL Assertions for Interface Specification2006 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2006.1692711(819-822)Online publication date: 2006
https://doi.org/10.1109/ISCAS.2006.1692711
Poulakis IEconomakos GTsanakas P(2000)Interaction in language based system level design using an advanced compiler generator environmentProceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era10.1109/IWV.2000.844536(97-102)Online publication date: 2000
https://doi.org/10.1109/IWV.2000.844536

Index Terms

The attributed-behavior abstraction and synthesis tools
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
  2. Very large scale integration design
2. Theory of computation
  1. Randomness, geometry and discrete structures

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Published In

cover image ACM Conferences

DAC '94: Proceedings of the 31st annual Design Automation Conference

June 1994

739 pages

ISBN:0897916530

DOI:10.1145/196244

Chairman:
Michael Lorenzetti
Mentor Graphics Corp., Wilsonville, OR

Copyright © 1994 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 June 1994

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DAC94: The 31st ACM/IEEE-CAS/EDAC Design Automation Conference

June 6 - 10, 1994

California, San Diego, USA

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DAC '94 Paper Acceptance Rate 100 of 260 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Economakos G(2006)Behavioral Synthesis with SystemC and PSL Assertions for Interface Specification2006 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2006.1692711(819-822)Online publication date: 2006
https://doi.org/10.1109/ISCAS.2006.1692711
Poulakis IEconomakos GTsanakas P(2000)Interaction in language based system level design using an advanced compiler generator environmentProceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era10.1109/IWV.2000.844536(97-102)Online publication date: 2000
https://doi.org/10.1109/IWV.2000.844536

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