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On testing wave pipelined circuits

Authors:

Jui-Ching Shyur,

Hung-Pin Chen,

Tai-Ming ParngAuthors Info & Claims

DAC '94: Proceedings of the 31st annual Design Automation Conference

Pages 370 - 374

https://doi.org/10.1145/196244.196425

Published: 06 June 1994 Publication History

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Cited By

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Zhang GLi BHuang XYin XZhuo CHashimoto MSchlichtmann U(2022)VirtualSync+: Timing Optimization With Virtual SynchronizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.315343341:12(5526-5540)Online publication date: Dec-2022
https://doi.org/10.1109/TCAD.2022.3153433
Tao Feng Noh-Jin Park Minsu Choi Nohpill Park (2010)Reliability Modeling and Analysis of Clockless Wave Pipeline Core for Embedded Combinational Logic DesignIEEE Transactions on Instrumentation and Measurement10.1109/TIM.2009.203091759:7(1812-1824)Online publication date: Jul-2010
https://doi.org/10.1109/TIM.2009.2030917
Teehan PLemieux GGreenstreet M(2009)Estimating reliability and throughput of source-synchronous wave-pipelined interconnectProceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip10.1109/NOCS.2009.5071472(234-243)Online publication date: 10-May-2009
https://dl.acm.org/doi/10.1109/NOCS.2009.5071472
Show More Cited By

Index Terms

On testing wave pipelined circuits
1. Hardware
  1. Hardware test
    1. Design for testability
  2. Integrated circuits
    1. Logic circuits
      1. Combinational circuits

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Published In

DAC '94: Proceedings of the 31st annual Design Automation Conference

June 1994

739 pages

ISBN:0897916530

DOI:10.1145/196244

Chairman:
Michael Lorenzetti
Mentor Graphics Corp., Wilsonville, OR

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 06 June 1994

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DAC94: The 31st ACM/IEEE-CAS/EDAC Design Automation Conference

June 6 - 10, 1994

California, San Diego, USA

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DAC '94 Paper Acceptance Rate 100 of 260 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Zhang GLi BHuang XYin XZhuo CHashimoto MSchlichtmann U(2022)VirtualSync+: Timing Optimization With Virtual SynchronizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.315343341:12(5526-5540)Online publication date: Dec-2022
https://doi.org/10.1109/TCAD.2022.3153433
Tao Feng Noh-Jin Park Minsu Choi Nohpill Park (2010)Reliability Modeling and Analysis of Clockless Wave Pipeline Core for Embedded Combinational Logic DesignIEEE Transactions on Instrumentation and Measurement10.1109/TIM.2009.203091759:7(1812-1824)Online publication date: Jul-2010
https://doi.org/10.1109/TIM.2009.2030917
Teehan PLemieux GGreenstreet M(2009)Estimating reliability and throughput of source-synchronous wave-pipelined interconnectProceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip10.1109/NOCS.2009.5071472(234-243)Online publication date: 10-May-2009
https://dl.acm.org/doi/10.1109/NOCS.2009.5071472
Feng TJin BWang JPark NKim YLombardi FVassiliadis SGaudiot JPiuri V(2004)Fault tolerant clockless wave pipeline designProceedings of the 1st conference on Computing frontiers10.1145/977091.977142(350-356)Online publication date: 14-Apr-2004
https://dl.acm.org/doi/10.1145/977091.977142
Feng TJin BPark NLombardi F(2004)Yield optimization of clockless wave pipeline with intra/inter-wave faultsProceedings of the 21st IEEE Instrumentation and Measurement Technology Conference (IEEE Cat. No.04CH37510)10.1109/IMTC.2004.1351347(1484-1489)Online publication date: 2004
https://doi.org/10.1109/IMTC.2004.1351347
Feng TPark NKim YLombardi FMeyer F(2004)Reliability modeling and assurance of clockless wave pipeline19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings.10.1109/DFTVS.2004.1347869(442-450)Online publication date: 2004
https://doi.org/10.1109/DFTVS.2004.1347869
Feng TPark NKim YPiuri V(2003)Yield modeling and analysis of a clockless asynchronous wave pipeline with pulse faultsProceedings. 16th IEEE Symposium on Computer Arithmetic10.1109/DFTVS.2003.1250093(34-41)Online publication date: 2003
https://doi.org/10.1109/DFTVS.2003.1250093
Martinez-Smith ASridhar R(1996)On-line detection of environmentally-induced delay faults in CMOS wave pipelined circuitsProceedings Ninth Annual IEEE International ASIC Conference and Exhibit10.1109/ASIC.1996.551963(57-60)Online publication date: 1996
https://doi.org/10.1109/ASIC.1996.551963

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Testing high-performance pipelined circuits with slow-speed testers

DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers

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