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Incorporating speculative execution in exact control-dependent scheduling

Authors:

Ivan Radivojevic,

Forrest BrewerAuthors Info & Claims

DAC '94: Proceedings of the 31st annual Design Automation Conference

Pages 479 - 484

https://doi.org/10.1145/196244.196473

Published: 06 June 1994 Publication History

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Cited By

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Alle MMorvan ADerrien S(2013)Runtime dependency analysis for loop pipelining in high-level synthesisProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488796(1-10)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488796
Jówiak LNedjah NFigueroa M(2010)Modern development methods and tools for embedded reconfigurable systemsIntegration, the VLSI Journal10.1016/j.vlsi.2009.06.00243:1(1-33)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1016/j.vlsi.2009.06.002
Chuck Monahan (2006)Symbolic Modeling and Evaluation of Data Paths32nd Design Automation Conference10.1109/DAC.1995.249979(389-394)Online publication date: Dec-2006
https://doi.org/10.1109/DAC.1995.249979
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Index Terms

Incorporating speculative execution in exact control-dependent scheduling
1. Hardware
  1. Integrated circuits
    1. Logic circuits

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Published In

DAC '94: Proceedings of the 31st annual Design Automation Conference

June 1994

739 pages

ISBN:0897916530

DOI:10.1145/196244

Chairman:
Michael Lorenzetti
Mentor Graphics Corp., Wilsonville, OR

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 06 June 1994

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DAC94: The 31st ACM/IEEE-CAS/EDAC Design Automation Conference

June 6 - 10, 1994

California, San Diego, USA

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DAC '94 Paper Acceptance Rate 100 of 260 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Alle MMorvan ADerrien S(2013)Runtime dependency analysis for loop pipelining in high-level synthesisProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488796(1-10)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488796
Jówiak LNedjah NFigueroa M(2010)Modern development methods and tools for embedded reconfigurable systemsIntegration, the VLSI Journal10.1016/j.vlsi.2009.06.00243:1(1-33)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1016/j.vlsi.2009.06.002
Chuck Monahan (2006)Symbolic Modeling and Evaluation of Data Paths32nd Design Automation Conference10.1109/DAC.1995.249979(389-394)Online publication date: Dec-2006
https://doi.org/10.1109/DAC.1995.249979
Kuchcinski KWolinski C(2003)Global approach to assignment and scheduling of complex behaviors based on HCDG and constraint programmingJournal of Systems Architecture: the EUROMICRO Journal10.1016/S1383-7621(03)00075-449:12-15(489-503)Online publication date: 1-Dec-2003
https://dl.acm.org/doi/10.1016/S1383-7621%2803%2900075-4
Memik SFallah F(2002)Accelerated SAT-based scheduling of control/data flow graphsProceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors10.1109/ICCD.2002.1106801(395-400)Online publication date: 2002
https://doi.org/10.1109/ICCD.2002.1106801
Kuchcinski KWolinski C(2001)Synthesis of conditional behaviors using hierarchical conditional dependency graphs and constraint logic programmingProceedings Euromicro Symposium on Digital Systems Design10.1109/DSD.2001.952285(220-227)Online publication date: 2001
https://doi.org/10.1109/DSD.2001.952285
Kountouris AWolinski CLe Lann J(2001)High-level synthesis using hierarchical conditional dependency graphs in the CODESIS systemJournal of Systems Architecture10.1016/S1383-7621(00)00051-547:3-4(293-313)Online publication date: Apr-2001
https://doi.org/10.1016/S1383-7621(00)00051-5
Kountouris AWolinski CKurdahi FHermida R(2000)Hierarchical conditional dependency graphs as a unifying design representation in the CODESIS high-level synthesis systemProceedings of the 13th international symposium on System synthesis10.5555/501790.501808(66-71)Online publication date: 20-Sep-2000
https://dl.acm.org/doi/10.5555/501790.501808
Chung KKim TLiu CSarrafzadeh MBanerjee PRoy K(2000)Behavioral-level partitioning for low power design in control-dominated applicationProceedings of the 10th Great Lakes symposium on VLSI10.1145/330855.331028(156-161)Online publication date: 2-Mar-2000
https://dl.acm.org/doi/10.1145/330855.331028
Kountouris AWolinski C(2000)Hierarchical conditional dependency graphs as a unifying design representation in the CODESIS high-level synthesis systemProceedings 13th International Symposium on System Synthesis10.1109/ISSS.2000.874030(66-71)Online publication date: 2000
https://doi.org/10.1109/ISSS.2000.874030
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