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Clock skew minimization during FPGA placement

Authors:

Kai Zhu,

D. F. WongAuthors Info & Claims

DAC '94: Proceedings of the 31st annual Design Automation Conference

Pages 232 - 237

https://doi.org/10.1145/196244.196362

Published: 06 June 1994 Publication History

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Cited By

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Li LLai J(2015)Design and implementation of clock network for nanometer FPGAIEICE Electronics Express10.1587/elex.12.2014118012:5(20141180-20141180)Online publication date: 2015
https://doi.org/10.1587/elex.12.20141180
Navarro DBarragan LArtigas JUrriza ILucia OJimenez O(2010)FPGA-based high resolution synchronous digital pulse width modulator2010 IEEE International Symposium on Industrial Electronics10.1109/ISIE.2010.5636571(2771-2776)Online publication date: Jul-2010
https://doi.org/10.1109/ISIE.2010.5636571
Lamoureux JWilton SWilton SDeHon A(2006)FPGA clock network architectureProceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays10.1145/1117201.1117216(101-108)Online publication date: 22-Feb-2006
https://dl.acm.org/doi/10.1145/1117201.1117216
Show More Cited By

Index Terms

Clock skew minimization during FPGA placement
1. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Combinational circuits
  2. Very large scale integration design
    1. Application-specific VLSI designs
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory
      1. Trees

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Published In

DAC '94: Proceedings of the 31st annual Design Automation Conference

June 1994

739 pages

ISBN:0897916530

DOI:10.1145/196244

Chairman:
Michael Lorenzetti
Mentor Graphics Corp., Wilsonville, OR

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 June 1994

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DAC94

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EDAC
SIGDA
IEEE-CAS

DAC94: The 31st ACM/IEEE-CAS/EDAC Design Automation Conference

June 6 - 10, 1994

California, San Diego, USA

Acceptance Rates

DAC '94 Paper Acceptance Rate 100 of 260 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Li LLai J(2015)Design and implementation of clock network for nanometer FPGAIEICE Electronics Express10.1587/elex.12.2014118012:5(20141180-20141180)Online publication date: 2015
https://doi.org/10.1587/elex.12.20141180
Navarro DBarragan LArtigas JUrriza ILucia OJimenez O(2010)FPGA-based high resolution synchronous digital pulse width modulator2010 IEEE International Symposium on Industrial Electronics10.1109/ISIE.2010.5636571(2771-2776)Online publication date: Jul-2010
https://doi.org/10.1109/ISIE.2010.5636571
Lamoureux JWilton SWilton SDeHon A(2006)FPGA clock network architectureProceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays10.1145/1117201.1117216(101-108)Online publication date: 22-Feb-2006
https://dl.acm.org/doi/10.1145/1117201.1117216
Lamoureux JWilton S(2006)Architecture and CAD for FPGA Clock Networks2006 International Conference on Field Programmable Logic and Applications10.1109/FPL.2006.311357(1-2)Online publication date: Aug-2006
https://doi.org/10.1109/FPL.2006.311357
Stohmann JBarke E(2005)An universal CLA adder generator for SRAM-based FPGAsField-Programmable Logic Smart Applications, New Paradigms and Compilers10.1007/3-540-61730-2_5(44-54)Online publication date: 6-Jun-2005
https://doi.org/10.1007/3-540-61730-2_5
Natesan VBhatia D(1996)Clock-Skew Constrained Cell PlacementProceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication10.5555/525699.834749Online publication date: 3-Jan-1996
https://dl.acm.org/doi/10.5555/525699.834749
Taegyu Lee Hoon Chung (1996)Timing optimization algorithm for design of high performance VLSI systems1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 9610.1109/ISCAS.1996.542002(465-468)Online publication date: 1996
https://doi.org/10.1109/ISCAS.1996.542002
Natesan VBhatia D(1995)Clock-skew constrained cell placementProceedings of 9th International Conference on VLSI Design10.1109/ICVD.1996.489474(146-149)Online publication date: 1995
https://doi.org/10.1109/ICVD.1996.489474

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