research-article

Xetal-Pro: an ultra-low energy and high throughput SIMD processor

Authors:

Yu Pu,

Sebastian M. Londono,

Henk CorporaalAuthors Info & Claims

DAC '10: Proceedings of the 47th Design Automation Conference

Pages 543 - 548

https://doi.org/10.1145/1837274.1837409

Published: 13 June 2010 Publication History

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Abstract

This paper presents Xetal-Pro SIMD processor, which is based on Xetal-II, one of the most computational-efficient (in terms of GOPS/Watt) processors available today. Xetal-Pro supports ultra wide V_DD scaling from nominal supply to the sub-threshold region. Although aggressive V_DD scaling causes severe throughput degradation, this can be compensated by the nature of massive parallelism in the Xetal family. The predecessor of Xetal-Pro, Xetal-II, includes a large on-chip frame memory (FM), which cannot operate reliably at ultra low voltage. Therefore we investigate both different FM realizations and memory organization alternatives. We propose a hybrid memory architecture which reduces the non-local memory traffic and enables further V_DD scaling. Compared to Xetal-II operating at nominal voltage, we could gain more than 10x energy reduction while still delivering a sufficiently high throughput of 0.69 GOPS (counting multiply and add operations only). This work gives a new insight to the design of ultra-low energy SIMD processors, which are suitable for portable streaming applications.

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Basu SDuch LPeon-Quiros MAtienza DAnsaloni GPozzi L(2018)Heterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications2018 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2018.8351595(1-5)Online publication date: May-2018
https://doi.org/10.1109/ISCAS.2018.8351595
Geng TDiken EWang TJozwiak LHerbordt M(2018)An Access-Pattern-Aware On-Chip Vector Memory System with Automatic Loading for SIMD Architectures2018 IEEE High Performance extreme Computing Conference (HPEC)10.1109/HPEC.2018.8547551(1-7)Online publication date: Sep-2018
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Basu SDuch LBraojos RAnsaloni GPozzi LAtienza D(2017)An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error RecoveryACM Transactions on Embedded Computing Systems10.1145/312656516:5s(1-19)Online publication date: 27-Sep-2017
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Index Terms

Xetal-Pro: an ultra-low energy and high throughput SIMD processor
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Single instruction, multiple data

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Information & Contributors

Information

Published In

DAC '10: Proceedings of the 47th Design Automation Conference

June 2010

1036 pages

ISBN:9781450300025

DOI:10.1145/1837274

General Chair:
Sachin Sapatnekar
Univ. of Minnesota, Minneapolis, MN

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2010

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DAC '10

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DAC '10: The 47th Annual Design Automation Conference 2010

June 13 - 18, 2010

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Basu SDuch LPeon-Quiros MAtienza DAnsaloni GPozzi L(2018)Heterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications2018 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2018.8351595(1-5)Online publication date: May-2018
https://doi.org/10.1109/ISCAS.2018.8351595
Geng TDiken EWang TJozwiak LHerbordt M(2018)An Access-Pattern-Aware On-Chip Vector Memory System with Automatic Loading for SIMD Architectures2018 IEEE High Performance extreme Computing Conference (HPEC)10.1109/HPEC.2018.8547551(1-7)Online publication date: Sep-2018
https://doi.org/10.1109/HPEC.2018.8547551
Basu SDuch LBraojos RAnsaloni GPozzi LAtienza D(2017)An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error RecoveryACM Transactions on Embedded Computing Systems10.1145/312656516:5s(1-19)Online publication date: 27-Sep-2017
https://dl.acm.org/doi/10.1145/3126565
Duch LBasu SBraojos RAnsaloni GPozzi LAtienza D(2017)HEAL-WEAR: An Ultra-Low Power Heterogeneous System for Bio-Signal AnalysisIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2017.270149964:9(2448-2461)Online publication date: Sep-2017
https://doi.org/10.1109/TCSI.2017.2701499
Braojos RBortolotti DBartolini AAnsaloni GBenini LAtienza D(2017)A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal ProcessingIEEE Transactions on Computers10.1109/TC.2016.261042666:4(575-585)Online publication date: 1-Apr-2017
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Braojos RAtienza DAly MWu TWong HMitra SAnsaloni G(2016)Nano-engineered architectures for ultra-low power wireless body sensor nodesProceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis10.1145/2968456.2968464(1-10)Online publication date: 1-Oct-2016
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He YPeemen MWaeijen LDiken EFiumara MRauwerda GCorporaal HGeng T(2016)A configurable SIMD architecture with explicit datapath for intelligent learning2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)10.1109/SAMOS.2016.7818343(156-163)Online publication date: Jul-2016
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Duch LBasu SBraojos RAtienza DAnsaloni GPozzi L(2016)A multi-core reconfigurable architecture for ultra-low power bio-signal analysis2016 IEEE Biomedical Circuits and Systems Conference (BioCAS)10.1109/BioCAS.2016.7833820(416-419)Online publication date: Oct-2016
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Fiorin LVermij Evan Lunteren JJongerius RHagleitner C(2016)Exploring the Design Space of an Energy-Efficient Accelerator for the SKA1-Low Central Signal ProcessorInternational Journal of Parallel Programming10.1007/s10766-016-0420-y44:5(1003-1027)Online publication date: 1-Apr-2016
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Xetal-II: A Low-Power Massively-Parallel Processor for Video Scene Analysis

From Xetal-II to Xetal-Pro: On the Road Toward an Ultralow-Energy and High-Throughput SIMD Processor

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