research-article

Who solves the variability problem?

Authors:

Christian Lütkemeyer,

Vijay Pitchumani,

Andrzej Strojwas,

Steve TrimbergerAuthors Info & Claims

DAC '10: Proceedings of the 47th Design Automation Conference

Pages 218 - 219

https://doi.org/10.1145/1837274.1837328

Published: 13 June 2010 Publication History

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Abstract

Although innovations in manufacturing technology help in reducing variations, IC design variations are a fact of life. In addition to random variations, systematic stress induced variations are becoming increasingly important. This panel will bring the diverse views from academia, foundries, fabless and IDM communities to address various topics on next generation solutions for variability, with the main emphasis on design and architecture solutions. Specifically, this panel will discuss:

• Would new architectures mitigate variability in 22nm and beyond?

• Could design regularity effectively mitigate variability?

• What design techniques can be used to minimize variability 'on-the-fly'?

• What new techniques can be used for memories, register arrays and flip-flops?

Who solves the variability problem?
1. Hardware

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Information & Contributors

Information

Published In

DAC '10: Proceedings of the 47th Design Automation Conference

June 2010

1036 pages

ISBN:9781450300025

DOI:10.1145/1837274

General Chair:
Sachin Sapatnekar
Univ. of Minnesota, Minneapolis, MN

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2010

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Author Tag

IC variability

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Research-article

Conference

DAC '10

Sponsor:

EDAC
SIGDA

DAC '10: The 47th Annual Design Automation Conference 2010

June 13 - 18, 2010

California, Anaheim

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Fin shape dependent variability for strained SOI FinFETs

Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era

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