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Orthrus: efficient software integrity protection on multi-cores

Published: 13 March 2010 Publication History

Abstract

This paper proposes an efficient hardware/software system that significantly enhances software security through diversified replication on multi-cores. Recent studies show that a large class of software attacks can be detected by running multiple versions of a program simultaneously and checking the consistency of their behaviors. However, execution of multiple replicas incurs significant overheads on today's computing platforms, especially with fine-grained comparisons necessary for high security. Orthrus exploits similarities in automatically generated replicas to enable simultaneous execution of those replicas with minimal overheads; the architecture reduces memory and bandwidth overheads by compressing multiple memory spaces together, and additional power consumption and silicon area by eliminating redundant computations. Utilizing the hardware architecture, Orthrus implements a fine-grained memory layout diversification with the LLVM compiler and can detect corruptions in both pointers and critical data. Experiments indicate that the Orthrus architecture incurs minimal overheads and provides a protection against a broad range of attacks.

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  • (2015)Reliable Integrity Checking in Multicore ProcessorsACM Transactions on Architecture and Code Optimization10.1145/273805212:2(1-23)Online publication date: 11-May-2015
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Published In

cover image ACM Conferences
ASPLOS XV: Proceedings of the fifteenth International Conference on Architectural support for programming languages and operating systems
March 2010
422 pages
ISBN:9781605588391
DOI:10.1145/1736020
  • General Chair:
  • James C. Hoe,
  • Program Chair:
  • Vikram S. Adve
  • cover image ACM SIGARCH Computer Architecture News
    ACM SIGARCH Computer Architecture News  Volume 38, Issue 1
    ASPLOS '10
    March 2010
    399 pages
    ISSN:0163-5964
    DOI:10.1145/1735970
    Issue’s Table of Contents
  • cover image ACM SIGPLAN Notices
    ACM SIGPLAN Notices  Volume 45, Issue 3
    ASPLOS '10
    March 2010
    399 pages
    ISSN:0362-1340
    EISSN:1558-1160
    DOI:10.1145/1735971
    Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 13 March 2010

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Author Tags

  1. memory protection
  2. multi-core architecture
  3. replication-aware architecture
  4. software diversity and redundancy
  5. software security

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ASPLOS XV Paper Acceptance Rate 32 of 181 submissions, 18%;
Overall Acceptance Rate 535 of 2,713 submissions, 20%

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Cited By

View all
  • (2015)Reliable Integrity Checking in Multicore ProcessorsACM Transactions on Architecture and Code Optimization10.1145/273805212:2(1-23)Online publication date: 11-May-2015
  • (2014)Programmable decoder and shadow threadsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616669(1-6)Online publication date: 24-Mar-2014
  • (2014)Continuous, Low Overhead, Run-Time Validation of Program ExecutionsProceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2014.18(229-241)Online publication date: 13-Dec-2014
  • (2013)Run-time control flow authenticationProceedings of the 28th Annual ACM Symposium on Applied Computing10.1145/2480362.2480708(1859-1866)Online publication date: 18-Mar-2013
  • (2012)Logical inference techniques for loop parallelizationACM SIGPLAN Notices10.1145/2345156.225412447:6(509-520)Online publication date: 11-Jun-2012
  • (2012)Polyhedra scanning revisitedACM SIGPLAN Notices10.1145/2345156.225412347:6(499-508)Online publication date: 11-Jun-2012
  • (2012)Effective parallelization of loops in the presence of I/O operationsACM SIGPLAN Notices10.1145/2345156.225412247:6(487-498)Online publication date: 11-Jun-2012
  • (2012)Static analysis and compiler design for idempotent processingACM SIGPLAN Notices10.1145/2345156.225412047:6(475-486)Online publication date: 11-Jun-2012
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  • (2012)ChimeraProceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/2254064.2254119(463-474)Online publication date: 11-Jun-2012
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