research-article

Architecture for dense matrix multiplication on a high-performance reconfigurable system

Authors:

Viviane L. S. de Souza,

Victor W. C. de Medeiros,

Manoel E. de LimaAuthors Info & Claims

SBCCI '09: Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

Article No.: 42, Pages 1 - 6

https://doi.org/10.1145/1601896.1601950

Published: 31 August 2009 Publication History

Abstract

The recent evolution of the programmable logic devices, such as FPGAs (Field Programmable Gate Array), associated with the growing demand for performance improvements in scientific computing applications, has attracted the attention of supercomputers vendors. They have been developing hybrid platforms that links general-purpose processors with co-processors based on FPGAs, aiming computing acceleration.

In this work we present the analysis and development of an important scientific computing operation: matrix multiplication, targeting the commercial hybrid platform RASC (Reconfigurable Application-Specific Computing), developed by Silicon Graphics.

The proposed architecture aims to reach better performance than conventional architectures, dissipating less power. To achieve this goal, we investigated the possibilities of implementation in parallel and data reuse intrinsic to the algorithm. Based on this investigation we propose a case study that uses the available resources in the target platform to explore these features.

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Barros, A. C., Medeiros, V. W., Souza, V. L., Nascimento, P. S., Mazer, Â., Barbosa, J. P., Neves, B. P., Santos, I., and de Lima, M. E. 2008. Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA. In Proceedings of the 21st Annual Symposium on integrated Circuits and System Design (Gramado, Brazil, September 01--04, 2008). SBCCI '08. ACM, New York, NY, 40--45.

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Cited By

Holanda BPimentel RBarbosa JCamarotti RSilva-Filho AJoao LSouza VFerraz JLima M(2011)An FPGA-Based Accelerator to Speed-Up Matrix Multiplication of Floating Point OperationsProceedings of the 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum10.1109/IPDPS.2011.165(306-309)Online publication date: 16-May-2011
https://dl.acm.org/doi/10.1109/IPDPS.2011.165
do A. Ferreira Ada S. Barros E(2010)A high performance full pipelined arquitecture of MLP Neural Networks in FPGA2010 17th IEEE International Conference on Electronics, Circuits and Systems10.1109/ICECS.2010.5724619(742-745)Online publication date: Dec-2010
https://doi.org/10.1109/ICECS.2010.5724619

Index Terms

Architecture for dense matrix multiplication on a high-performance reconfigurable system

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Published In

cover image ACM Conferences

SBCCI '09: Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

August 2009

325 pages

ISBN:9781605587059

DOI:10.1145/1601896

General Chair:
Ivan Saraiva
UFRN, Brazil
,
Program Chairs:
Renato Perez Ribas
UFRGS, Brazil
,
Calvin Plett
Carleton University, Canada

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SBC: Brazilian Computer Society
SIGDA: ACM Special Interest Group on Design Automation
SBMICRO: Brazilian Microelectronics Society
IEEE Circuits & Systems Society

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 31 August 2009

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SBCCI '09

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SBC
SIGDA
SBMICRO

SBCCI '09: 22nd Symposium on Integrated Circuits and System Design

August 31 - September 3, 2009

Natal, Brazil

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SBCCI '09 Paper Acceptance Rate 50 of 119 submissions, 42%;

Overall Acceptance Rate 133 of 347 submissions, 38%

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Cited By

Holanda BPimentel RBarbosa JCamarotti RSilva-Filho AJoao LSouza VFerraz JLima M(2011)An FPGA-Based Accelerator to Speed-Up Matrix Multiplication of Floating Point OperationsProceedings of the 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum10.1109/IPDPS.2011.165(306-309)Online publication date: 16-May-2011
https://dl.acm.org/doi/10.1109/IPDPS.2011.165
do A. Ferreira Ada S. Barros E(2010)A high performance full pipelined arquitecture of MLP Neural Networks in FPGA2010 17th IEEE International Conference on Electronics, Circuits and Systems10.1109/ICECS.2010.5724619(742-745)Online publication date: Dec-2010
https://doi.org/10.1109/ICECS.2010.5724619

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