research-article

Memory organization and data layout for instruction set extensions with architecturally visible storage

Authors:

Panagiotis Athanasopoulos,

Philip Brisk,

Yusuf Leblebici,

Paolo IenneAuthors Info & Claims

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

Pages 689 - 696

https://doi.org/10.1145/1687399.1687527

Published: 02 November 2009 Publication History

Get Access

Abstract

Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional units (CFUs). Adoption of the optimal ISE for an application would, in many cases, impose formidable cost increase in order to achieve the required data bandwidth. In this paper we propose a novel methodology for laying out data in memories, generating high-bandwidth memory systems by making use of existing low-bandwidth low-cost ones and designing custom functional units all with the desirable data bandwidth for only a fraction of the additional cost required by traditional techniques.

References

[1]

Biswas, P., Choudhary, V., Atasu, K., Pozzi, L., Ienne, P., and Dutt, N. 2004. Introduction of local memory elements in instruction set extensions. In Proceedings of the 41st Annual Conference on Design Automation (San Diego, CA, USA, June 07--11, 2004). DAC '04. ACM, New York, NY, 729--734. DOI= http://doi.acm.org/10.1145/996566.996765.

Digital Library

Google Scholar

[2]

Biswas, P., Dutt, N., Pozzi, L. and Ienne, P. Introduction of architecturally visible storage in instruction set extensions. IEEE Trans. CAD 26, 3 (Mar. 2007), 435--446. DOI = http://dx.doi.org/10.1109/TCAD.2006.890582.

Digital Library

Google Scholar

[3]

Clark, N., Zhong, H., and Mahlke, S. Automated custom instruction generation for domain-specific processor acceleration. IEEE Trans. Computers 54, 10 (Oct. 2005), 1258--1270. DOI= http://doi.ieeecomputersociety.org/10.1109/TC.2005.156.

Digital Library

Google Scholar

[4]

Karuri, K., Chattopadhyay, A., Hohenauer, M., Leupers, R., Ascheid, G., and Meyr, H. 2007. Increasing data-bandwidth to instruction-set extensions through register clustering. In Proceedings of the 2007 IEEE/ACM international Conference on Computer-Aided Design (San Jose, California, November 05--08, 2007). International Conference on Computer Aided Design. IEEE Press, Piscataway, NJ, 166--171. DOI= http://doi.acm.org/10.1145/1326073.1326108.

Digital Library

Google Scholar

[5]

Kluter, T., Brisk, P., Ienne, P., and Charbon, E. 2008. Speculative DMA for architecturally visible storage in instruction set extensions. In Proceedings of the 6th IEEE/ACM/IFIP international Conference on Hardware/Software Codesign and System Synthesis (Atlanta, GA, USA, October 19--24, 2008). CODES/ISSS'08. ACM, New York, NY, 243--248. DOI= http://doi.acm.org/10.1145/1450135.1450191.

Digital Library

Google Scholar

[6]

Morton, G. M., 1966. A computer oriented geodetic data base; and a new technique in file sequencing. Technical Report, IBM Ltd., Ottawa, Canada.

Google Scholar

[7]

Panda, P. R., Catthoor, F., Dutt, N. D., Danckaert, K., Brockmeyer, E., Kulkarni, C., Vandercappelle, A., and Kjeldsberg, P. G. 2001. Data and memory optimization techniques for embedded systems. ACM Trans. Des. Autom. Electron. Syst. 6, 2 (Apr. 2001), 149--206. DOI= http://doi.acm.org/10.1145/375977.375978.

Digital Library

Google Scholar

[8]

Pangrle, B. M. On the complexity of connectivity binding. IEEE Trans. CAD 10, 11 (Nov. 1991), 1460--1465. DOI= http://doi.ieeecomputersociety.org/10.1109/43.97625.

Digital Library

Google Scholar

[9]

Pozzi, L., Atasu, K., and Ienne, P. Exact and approximate algorithms for the extension of embedded processor instruction sets. IEEE Trans. CAD 25, 7 (Jul. 2006), 1209--1229. DOI= http://doi.ieeecomputersociety.org/10.1109/TCAD.2005.855950.

Digital Library

Google Scholar

[10]

Pozzi, L. and Ienne, P. 2005. Exploiting pipelining to relax registerfile port constraints of instruction-set extensions. In Proceedings of the 2005 international Conference on Compilers, Architectures and Synthesis For Embedded Systems (San Francisco, California, USA, September 24--27, 2005). CASES '05. ACM, New York, NY, 2--10. DOI= http://doi.acm.org/10.1145/1086297.1086300.

Digital Library

Google Scholar

[11]

Schmit, H., and Thomas, D. E. Synthesis of application-specific memory designs. IEEE Trans. VLSI 5, 1 (May 1997) 101--111. DOI= http://doi.ieeecomputersociety.org/10.1109/92.555990.

Digital Library

Google Scholar

[12]

Sun, F., Ravi, S., Raghunathan, A., and Jha, N. K. Custom-instruction synthesis for extensible processor platforms. IEEE Trans. CAD 23, 2 (Feb. 2004), 216--228. DOI= http://doi.ieeecomputersociety.org/10.1109/TCAD.2003.822133.

Digital Library

Google Scholar

[13]

Verma, A. K., Brisk, P., and Ienne, P. 2007. Rethinking custom ISE identification: a new processor-agnostic method. In Proceedings of the 2007 international Conference on Compilers, Architecture, and Synthesis For Embedded Systems (Salzburg, Austria, September 30 - October 03, 2007). CASES'07. ACM, New York, NY, 125--134. DOI= http://doi.acm.org/10.1145/1289881.1289905.

Digital Library

Google Scholar

Cited By

View all

Panda PSharma NPilania AKrishnaiah GSubramoney SJagannathan A(2014)Array scalarization in high level synthesis2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2014.6742960(622-627)Online publication date: Jan-2014
https://doi.org/10.1109/ASPDAC.2014.6742960

Index Terms

Memory organization and data layout for instruction set extensions with architecturally visible storage
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
  2. Integrated circuits
    1. Logic circuits
      1. Arithmetic and datapath circuits
    2. Semiconductor memory

Recommendations

Introduction of Architecturally Visible Storage in Instruction Set Extensions

Instruction set extensions (ISEs) can be used effectively to accelerate the performance of embedded processors. The critical and difficult task of ISE selection is often performed manually by designers. A few automatic methods for ISE generation have ...
Efficient resource utilization for an extensible processor through dynamic instruction set adaptation

State-of-the-art application-specific instruction set processors (ASIPs) allow the designer to define individual prefabrication customizations, thus improving the degree of specialization towards the actual application requirements, e.g., the ...
Exploiting forwarding to improve data bandwidth of instruction-set extensions
DAC '06: Proceedings of the 43rd annual Design Automation Conference

Application-specific instruction-set extensions (custom instructions) help embedded processors achieve higher performance. Most custom instructions offering significant performance benefit require multiple input operands. Unfortunately, RISC-style ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

November 2009

803 pages

ISBN:9781605588001

DOI:10.1145/1687399

General Chair:
Jaijeet Roychowdhury
Univ. of California, Berkeley, Berkeley, California

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 November 2009

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

ICCAD '09

Sponsor:

SIGDA

ICCAD '09: The International Conference on Computer-Aided Design

November 2 - 5, 2009

California, San Jose

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

1
Total Citations
View Citations
98
Total Downloads

Downloads (Last 12 months)1
Downloads (Last 6 weeks)0

Reflects downloads up to 17 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Panda PSharma NPilania AKrishnaiah GSubramoney SJagannathan A(2014)Array scalarization in high level synthesis2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2014.6742960(622-627)Online publication date: Jan-2014
https://doi.org/10.1109/ASPDAC.2014.6742960

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Introduction of Architecturally Visible Storage in Instruction Set Extensions

Efficient resource utilization for an extensible processor through dynamic instruction set adaptation

Exploiting forwarding to improve data bandwidth of instruction-set extensions