research-article

Dynamic context management for low power coarse-grained reconfigurable architecture

Authors:

Yoonjin Kim,

Rabi N. MahapatraAuthors Info & Claims

GLSVLSI '09: Proceedings of the 19th ACM Great Lakes symposium on VLSI

Pages 33 - 38

https://doi.org/10.1145/1531542.1531555

Published: 10 May 2009 Publication History

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Abstract

Coarse-grained reconfigurable architectures (CGRA) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array. Al-though this structure is meant for high performance and flexibility, it consumes significant power. Specially, power consumption by configuration cache is explicit overhead compared to other types of IP cores. Reducing power in configuration cache is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. In this paper, we propose a dynamic context management strategy for power saving in configuration cache. This power-efficient approach works without degrading the per-formance and flexibility of CGRA. Experimental results show that the proposed approach saves 38.24%/38.15% of the power in write/read-operation of configuration cache with negligible area overhead compared to the previous design.

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Cited By

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Ko YKang JLee JKim YKim JSo HLee KPaek Y(2016)Software-Based Selective Validation Techniques for Robust CGRAs Against Soft ErrorsACM Transactions on Embedded Computing Systems (TECS)10.1145/284394315:1(1-26)Online publication date: 28-Jan-2016
https://dl.acm.org/doi/10.1145/2843943
Horváth ILi YRusák Zvan der Vegte WZhang G(2016)Dynamic Computation of Time-Varying Spatial ContextsJournal of Computing and Information Science in Engineering10.1115/1.403403417:1(011007)Online publication date: 7-Nov-2016
https://doi.org/10.1115/1.4034034
Lari VLARI V(2016)IntroductionInvasive Tightly Coupled Processor Arrays10.1007/978-981-10-1058-3_1(1-19)Online publication date: 9-Jul-2016
https://doi.org/10.1007/978-981-10-1058-3_1
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Index Terms

Dynamic context management for low power coarse-grained reconfigurable architecture
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems
2. Hardware
  1. Communication hardware, interfaces and storage
    1. Signal processing systems

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Information & Contributors

Information

Published In

GLSVLSI '09: Proceedings of the 19th ACM Great Lakes symposium on VLSI

May 2009

558 pages

ISBN:9781605585222

DOI:10.1145/1531542

Co-chair:
Fabrizio Lombardi,
General Chairs:
Sanjukta Bhanja
University of South Florida, USA
,
Yehia Massoud
Rice University, USA
,
Program Chair:
R. Iris Bahar
Brown University, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 May 2009

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GLSVLSI '09

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GLSVLSI '09: Great Lakes Symposium on VLSI 2009

May 10 - 12, 2009

MA, Boston Area, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

View all

Ko YKang JLee JKim YKim JSo HLee KPaek Y(2016)Software-Based Selective Validation Techniques for Robust CGRAs Against Soft ErrorsACM Transactions on Embedded Computing Systems (TECS)10.1145/284394315:1(1-26)Online publication date: 28-Jan-2016
https://dl.acm.org/doi/10.1145/2843943
Horváth ILi YRusák Zvan der Vegte WZhang G(2016)Dynamic Computation of Time-Varying Spatial ContextsJournal of Computing and Information Science in Engineering10.1115/1.403403417:1(011007)Online publication date: 7-Nov-2016
https://doi.org/10.1115/1.4034034
Lari VLARI V(2016)IntroductionInvasive Tightly Coupled Processor Arrays10.1007/978-981-10-1058-3_1(1-19)Online publication date: 9-Jul-2016
https://doi.org/10.1007/978-981-10-1058-3_1
Schulz SBringmann OSchweizer TRosenstiel W(2014)Rotated parallel mapping: A novel approach for mapping data parallel applications on CGRAs2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)10.1109/ReConFig.2014.7032554(1-6)Online publication date: Dec-2014
https://doi.org/10.1109/ReConFig.2014.7032554
Kuuhn JSchweizer TPeterson DKuhn TRosenstiel W(2013)Testing reliability techniques for SoCs with fault tolerant CGRA by using live FPGA fault injection2013 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2013.6718415(462-465)Online publication date: Dec-2013
https://doi.org/10.1109/FPT.2013.6718415
Schweizer TKuster AEisenhardt SKuhn TRosenstiel W(2012)Using Run-Time Reconfiguration to Implement Fault-Tolerant Coarse Grained Reconfigurable ArchitecturesProceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum10.1109/IPDPSW.2012.39(320-327)Online publication date: 21-May-2012
https://dl.acm.org/doi/10.1109/IPDPSW.2012.39
Cao PCai YLiu BShan W(2012)Configuration Cache Management for Coarse-Grained Reconfigurable Architecture with Multi-ArrayProceedings of the 2012 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery10.1109/CyberC.2012.55(286-291)Online publication date: 10-Oct-2012
https://dl.acm.org/doi/10.1109/CyberC.2012.55
Mahapatra R(2011)BibliographyDesign of Low-Power Coarse-Grained Reconfigurable Architectures10.1201/b10471-13(189-196)Online publication date: 14-Apr-2011
https://doi.org/10.1201/b10471-13
Schweizer TSchlicker PEisenhardt SKuhn TRosenstiel W(2011)Low-Cost TMR for Fault-Tolerance on Coarse-Grained Reconfigurable ArchitecturesProceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs10.1109/ReConFig.2011.57(135-140)Online publication date: 30-Nov-2011
https://dl.acm.org/doi/10.1109/ReConFig.2011.57
Yanliang Liu Peng Dai Xin'an Wang Xing Zhang Lai Wei Yan Zhou Yachun Sun (2009)Dynamic context management for coarse-grained reconfigurable array DSP architecture2009 IEEE 8th International Conference on ASIC10.1109/ASICON.2009.5351603(79-82)Online publication date: Oct-2009
https://doi.org/10.1109/ASICON.2009.5351603

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