research-article

End-to-end validation of architectural power models

Authors:

Madhu Saravana Sibi Govindan,

Stephen W. Keckler,

Doug BurgerAuthors Info & Claims

ISLPED '09: Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design

Pages 383 - 388

https://doi.org/10.1145/1594233.1594332

Published: 19 August 2009 Publication History

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Abstract

While researchers have invested substantial effort to build architectural power models, validating such models has proven difficult at best. In this paper, we examine the accuracy of commonly used architectural power models using the TRIPS system as a case study. We use the TRIPS processor because we have ready access to the TRIPS architectural simulators, RTL simulators, and hardware. Access to all three levels of the design provides key insights that are missing from previously published power validation studies. First, we show that applying common architectural power models out-of-the-box to TRIPS results in an underestimate of the total power by 65%. Next, using a detailed breakdown of an accurate RTL power model (6% average error), we identify and quantify the major sources of inaccuracies in the architectural power model. Finally, we show how fixing these sources of errors decreases the inaccuracy to 24%. While further reductions are difficult due to systematic modeling errors in the simulator, we conclude with recommendations on where to focus attention when building architectural power models.

References

[1]

W. L. Bircher, M. Valluri, J. Law, and L. K. John. Runtime Identification of Microprocessor Energy Saving Opportunities. In International Symposium on Low Power Electronics and Design, pages 275--280, August 2005.

Digital Library

[2]

D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A Framework for Architectural-level Power Analysis and Optimizations. In International Symposium on Computer architecture, pages 83--94, May 2000.

Digital Library

[3]

D. Burger, S. W. Keckler, K. S. McKinley, M. Dahlin, L. K. John, C. Lin, C. R. Moore, J. Burrill, R. G. McDonald, W. Yoder, and the TRIPS Team. Scaling to the End of Silicon with EDGE architectures. IEEE Computer, 37(7):44--55, July 2004.

Digital Library

[4]

R. Y. Chen, R. M. Owens, M. J. Irwin, and R. S. Bajwa. Validation of an Architectural Level Power Analysis Technique. In Design Automation Conference, pages 242--245, June 1998.

Digital Library

[5]

http://www.eembc.org.

[6]

J. Engel, T. Guzowksi, A. Hunt, D. Lackey, L. Pickup, R. Proctor, K. Reynolds, A. Rincon, and D. Stauffer. Design Methodology for IBM ASIC Products. IBM Journal of Research and Development, 40(4):387--406, July 1996.

Digital Library

[7]

C. Kim, D. Burger, and S. W. Keckler. An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches. In International Conference on Architectural Support for Programming Languages and Operating Systems, pages 211--222, October 2002.

Digital Library

[8]

N. S. Kim, T. Austin, T. Mudge, and D. Grunwald. Challenges for Architectural Level Power Modeling. In Power Aware Computing, pages 317--337. Kluwer Academic Publishers, Norwell, MA, 2002.

Digital Library

[9]

F. J. Mesa-Martinez, J. Nayfach-Battilana, and J. Renau. Power Model Validation Through Thermal Measurements. In International Symposium on Computer Architecture, pages 302--311, June 2007.

Digital Library

[10]

Micron Technology Incorporated. Calculating DDR Memory System Power. http://download.micron.com/pdf/technotes/ddr/TN4603.pdf.

[11]

F. N. Najm. A Survey of Power Estimation Techniques in VLSI circuits. IEEE Transactions on Very Large Scale Integrated Systems, 2(4):446--455, December 1994.

Digital Library

[12]

K. Natarajan, H. Hanson, S. W. Keckler, C. R. Moore, and D. Burger. Microprocessor Pipeline Energy Analysis. In International Symposium on Low Power Electronics and Design, pages 282--287, August 2003.

Digital Library

[13]

M. Nemani and F. Najm. High-level Area and Power Estimation for VLSI Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(6):697--713, June 1999.

Digital Library

[14]

H. Shafi, P. J. Bohrer, J. Phelan, C. A. Rusu, and J. L. Peterson. Design and Validation of a Performance and Power Simulator for PowerPC Systems. IBM Journal of Research and Development, 47(5/6):641--651, 2003.

Digital Library

[15]

D. Stroobandt and J. V. Campenhout. Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle. In VLSI Design, Special Issue on Physical Design in Deep Submicron, volume 10, pages 1--20, 1999.

[16]

Synopsys, Inc. PrimePower and VCS. www.synopsys.com.

[17]

D. Tarjan, S. Thoziyoor, and N. Jouppi. CACTI 4.0. Technical Report HPL-2006-86, HP Labs, 2006.

[18]

Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, and M. Stan. HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects. Technical Report CS-2003-05, University of Virginia, Department of Computer Science, March 2003.

Cited By

Xi SJacobson HBose PWei GBrooks D(2015)Quantifying sources of error in McPAT and potential impacts on architectural studies2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2015.7056064(577-589)Online publication date: Feb-2015
https://doi.org/10.1109/HPCA.2015.7056064
Sultan HAnanthanarayanan GSarangi S(2014)Processor power estimation techniquesInternational Journal of High Performance Systems Architecture10.1504/IJHPSA.2014.0614485:2(93-114)Online publication date: 1-May-2014
https://dl.acm.org/doi/10.1504/IJHPSA.2014.061448
Govindan MRobatmili BLi DMaher BSmith AKeckler SBurger D(2014)Scaling Power and Performance viaProcessor ComposabilityIEEE Transactions on Computers10.1109/TC.2013.4863:8(2025-2038)Online publication date: 1-Aug-2014
https://dl.acm.org/doi/10.1109/TC.2013.48
Show More Cited By

Index Terms

End-to-end validation of architectural power models
1. Hardware
  1. Electronic design automation
    1. Modeling and parameter extraction
  2. Hardware validation
    1. Functional verification
      1. Simulation and emulation

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Published In

cover image ACM Conferences

ISLPED '09: Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design

August 2009

452 pages

ISBN:9781605586847

DOI:10.1145/1594233

General Chairs:
Jörg Henkel
University of Karlsruhe
,
Ali Keshavarzi
Taiwan Semiconductor Manufacturing Company
,
Program Chairs:
Naehyuck Chang
Seoul National University
,
Tahir Ghani
Intel Corporation

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 19 August 2009

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ISLPED'09

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ISLPED'09: International Symposium on Low Power Electronics and Design

August 19 - 21, 2009

CA, San Fancisco, USA

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ISLPED '09 Paper Acceptance Rate 72 of 208 submissions, 35%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

Xi SJacobson HBose PWei GBrooks D(2015)Quantifying sources of error in McPAT and potential impacts on architectural studies2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2015.7056064(577-589)Online publication date: Feb-2015
https://doi.org/10.1109/HPCA.2015.7056064
Sultan HAnanthanarayanan GSarangi S(2014)Processor power estimation techniquesInternational Journal of High Performance Systems Architecture10.1504/IJHPSA.2014.0614485:2(93-114)Online publication date: 1-May-2014
https://dl.acm.org/doi/10.1504/IJHPSA.2014.061448
Govindan MRobatmili BLi DMaher BSmith AKeckler SBurger D(2014)Scaling Power and Performance viaProcessor ComposabilityIEEE Transactions on Computers10.1109/TC.2013.4863:8(2025-2038)Online publication date: 1-Aug-2014
https://dl.acm.org/doi/10.1109/TC.2013.48
Lockhart DZibrat GBatten CFlautner KWenisch TOzer EFerdman M(2014)PyMTLProceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2014.50(280-292)Online publication date: 13-Dec-2014
https://dl.acm.org/doi/10.1109/MICRO.2014.50
Goel BMcKee SSjälander M(2012)Techniques to Measure, Model, and Manage PowerAdvances in Computers Volume 8710.1016/B978-0-12-396528-8.00002-X(7-54)Online publication date: 2012
https://doi.org/10.1016/B978-0-12-396528-8.00002-X
Robatmili BGovindan SBurger DKeckler S(2011)Exploiting criticality to reduce bottlenecks in distributed uniprocessors2011 IEEE 17th International Symposium on High Performance Computer Architecture10.1109/HPCA.2011.5749749(431-442)Online publication date: Feb-2011
https://doi.org/10.1109/HPCA.2011.5749749
Jacobson HBuyuktosunoglu ABose PAcar EEickemeyer R(2011)Abstraction and microarchitecture scaling in early-stage power modeling2011 IEEE 17th International Symposium on High Performance Computer Architecture10.1109/HPCA.2011.5749746(394-405)Online publication date: Feb-2011
https://doi.org/10.1109/HPCA.2011.5749746

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