poster

Enabling ultra low voltage system operation by tolerating on-chip cache failures

Authors:

Amin Ansari,

Shuguang Feng,

Shantanu Gupta,

Scott MahlkeAuthors Info & Claims

ISLPED '09: Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design

Pages 307 - 310

https://doi.org/10.1145/1594233.1594309

Published: 19 August 2009 Publication History

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Abstract

Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely used technique to tackle this problem when high performance is not needed. However, the minimum achievable supply voltage is often bounded by SRAM cells since they fail at a faster rate than logic cells. In this work, we propose a novel fault-tolerant cache architecture, that by reconfiguring its internal organization can efficiently tolerate SRAM failures that arise when operating in the ultra low voltage region. Using our approach, the operational voltage of a processor can be reduced to 420mV, which translates to 80% dynamic and 73% leakage power savings in 90nm.

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Cited By

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Choudhury AMondal BPaul KSikdar B(2023)Energy efficiency in multicore shared cache by fault tolerance using a genetic algorithm based block reuse predictorMicroprocessors and Microsystems10.1016/j.micpro.2023.104864101(104864)Online publication date: Sep-2023
https://doi.org/10.1016/j.micpro.2023.104864
Isquierdo MSoares RSampaio FZatt BPalomino D(2023)VVC decoder intra prediction using approximate storage: an error resilience evaluationAnalog Integrated Circuits and Signal Processing10.1007/s10470-023-02189-1117:1-3(95-111)Online publication date: 1-Dec-2023
https://dl.acm.org/doi/10.1007/s10470-023-02189-1
Maity BDonyanavard BSurhonne ARahmani AHerkersdorf ADutt N(2021)SEAMSACM Transactions on Embedded Computing Systems10.1145/346687520:5(1-26)Online publication date: 29-Jul-2021
https://dl.acm.org/doi/10.1145/3466875
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Index Terms

Enabling ultra low voltage system operation by tolerating on-chip cache failures
1. Hardware
  1. Hardware test
    1. Memory test and repair

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Information & Contributors

Information

Published In

ISLPED '09: Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design

August 2009

452 pages

ISBN:9781605586847

DOI:10.1145/1594233

General Chairs:
Jörg Henkel
University of Karlsruhe
,
Ali Keshavarzi
Taiwan Semiconductor Manufacturing Company
,
Program Chairs:
Naehyuck Chang
Seoul National University
,
Tahir Ghani
Intel Corporation

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 August 2009

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ISLPED'09

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ISLPED'09: International Symposium on Low Power Electronics and Design

August 19 - 21, 2009

CA, San Fancisco, USA

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ISLPED '09 Paper Acceptance Rate 72 of 208 submissions, 35%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

View all

Choudhury AMondal BPaul KSikdar B(2023)Energy efficiency in multicore shared cache by fault tolerance using a genetic algorithm based block reuse predictorMicroprocessors and Microsystems10.1016/j.micpro.2023.104864101(104864)Online publication date: Sep-2023
https://doi.org/10.1016/j.micpro.2023.104864
Isquierdo MSoares RSampaio FZatt BPalomino D(2023)VVC decoder intra prediction using approximate storage: an error resilience evaluationAnalog Integrated Circuits and Signal Processing10.1007/s10470-023-02189-1117:1-3(95-111)Online publication date: 1-Dec-2023
https://dl.acm.org/doi/10.1007/s10470-023-02189-1
Maity BDonyanavard BSurhonne ARahmani AHerkersdorf ADutt N(2021)SEAMSACM Transactions on Embedded Computing Systems10.1145/346687520:5(1-26)Online publication date: 29-Jul-2021
https://dl.acm.org/doi/10.1145/3466875
Choudhury ASikdar B(2020)Modeling Remapping Based Fault Tolerance Techniques for Chip Multiprocessor Cache with Design Space ExplorationJournal of Electronic Testing10.1007/s10836-019-05852-6Online publication date: 18-Feb-2020
https://doi.org/10.1007/s10836-019-05852-6
Choudhury ASikdar B(2019)CORE-VR: A Coherence and Reusability Aware Low Voltage Fault Tolerant Cache in Multicore2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT.2019.8875457(1-4)Online publication date: Oct-2019
https://doi.org/10.1109/DFT.2019.8875457
Choudhury ASikdar B(2018)Modeling & Analysis of Redundancy Based Fault Tolerance for Permanent Faults in Chip Multiprocessor Cache2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2018.47(115-120)Online publication date: Jan-2018
https://doi.org/10.1109/VLSID.2018.47
Choudhury AMondal BSikdar B(2018)ReMiT: Redundancy Migration for Latency Aware Fault Tolerant Cache Design in Multicore2018 8th International Symposium on Embedded Computing and System Design (ISED)10.1109/ISED.2018.8704108(80-84)Online publication date: Dec-2018
https://doi.org/10.1109/ISED.2018.8704108
Marukame TUeyoshi KAsai TMotomura MSchmid ASuzuki MHigashi YMitani Y(2017)Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory ImplementationIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2016.258567564:4(462-466)Online publication date: Apr-2017
https://doi.org/10.1109/TCSII.2016.2585675
Choudhury ASikdar B(2017)CIFR: A complete in-place fault remapping strategy for CMP cache using dynamic reuse distance2017 7th International Symposium on Embedded Computing and System Design (ISED)10.1109/ISED.2017.8303922(1-5)Online publication date: Dec-2017
https://doi.org/10.1109/ISED.2017.8303922
Choudhury ASikdar B(2017)Performance Analysis of Disability Based Fault Tolerance Techniques for Permanent Faults in Chip MultiprocessorsVLSI Design and Test10.1007/978-981-10-7470-7_22(217-224)Online publication date: 21-Dec-2017
https://doi.org/10.1007/978-981-10-7470-7_22
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Using a Flexible Fault-Tolerant Cache to Improve Reliability for Ultra Low Voltage Operation

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